Insulated gate field-effect transistor and a method of manufacturing the same

Abstract

The invention aims at precisely making an effective junction depth sufficiently small with respect to a substrate surface having a steep PN junction stable in its configuration and having a channel formed therein in relation to an extension portion. Gate electrodes are formed on a P-type well and an N-type well through respective gate insulating films. Two extension portions are formed from two first epitaxial growth layers which contact regions, of the P-type well and the N-type well, where channels are to be formed, respectively, and which are at a distance from each other. Two second epitaxial growth layers are formed on the first epitaxial growth layers in positions which are further at a distance from facing ends of the two extension portions in a direction of being separate from each other. Thus, two source/drain regions are formed on a PMOS side and on an NMOS side each. In the case of this structure, there is adopted no ion implantation for introducing impurities into a deep portion. Hence, the impurities in the extension portions do not thermally diffuse into the substrate side through the activation anneal.

Description

CROSS REFERENCES TO RELATED APPLICATIONS [0001] The present invention contains subject matter related to Japanese Patent Application P2005-001608 filed in the Japanese Patent Office on Jan. 6, 2005, the entire contents of which being incorporated herein by reference. BACKGROUND OF THE INVENTION [0002] The present invention relates to an insulated gate field-effect transistor having an extension portion in each of two source / drain regions through which a current is supplied to a region of a semiconductor substrate which faces a gate electrode through a gate insulating film and which has a channel formed therein, and a method of manufacturing the same. [0003] With respect to the scaling of an insulated gate field-effect transistor (hereinafter referred to as “a MIS transistor”), in the International Technology Roadmap for Semiconductors (ITRS), a transistor gate length Lg of a technology node hp32 is expected to become equal to or shorter than 20 nm. [0004] In order to realize such a ...

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Benefits of technology

[0020] According to the present invention, the advantages are provided in which a steep PN junction having a stable configuration is formed below the source/drain region having the extens...

Problems solved by technology

However, the ion implantation technique and activation anneal technique for forming a very shallow junction which is applicable to the above-mentioned fine MIS transistor are not yet established.

In addition, even if the very shallow junction can be formed by utilizing the ion implantation method, owing to its thinness, its resistance value becomes large and a series resistance value of the source and the drain increases to reduce the driving ability of the MIS transistor.

However, this is inconsistent with the suppression of the short channel effect.

Hence, there is encountered a problem that a space is defined between the extension portion (the first source/drain region) and the channel layer and thus this space portion has a large resistance value in some...

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