The invention provides a TSV (
through silicon via) back side hole leaking technology without CMP (chemical mechanical
grinding) technology. The TSV back side hole leaking technology comprises the following steps of S1, providing a device
wafer which completes a front side technology, wherein the device
wafer comprises a substrate and a TSV (
through silicon via)
blind hole, and the TVS
blind hole is formed in the substrate; S2, providing a carrier
wafer, and bonding the front side of the device wafer and the carrier wafer by a temporary bonding technology, so as to obtain a temporary bonding body; S3, mechanically
grinding the back side of the substrate of the device wafer, and
thinning; S4,
etching the back side of the substrate, and enabling the TSV
blind hole to
expose out of the back side of the substrate; S5,
coating a back side medium layer at the back side of the substrate of the device wafer, and completely covering the exposing part of the TSV blind hole in the step S4; S6, utilizing a mechanical
grinding technology to process the back side medium layer, and enabling the TSV blind hole to
expose out of the back side medium layer. The TSV back side hole leaking technology has the advantages that the CMP process in the TSV back side end exposing process is avoided, the technological cost is greatly reduced, the output efficiency is obviously improved, and the self-aligning effect of the back side medium layer hole via is realized.