15 results about "Maximum latency" patented technology

The invention provides a maximum delay calculation method and device and a computer readable storage medium, relates to the technical field of integrated circuits, and is used for solving the problem of how to improve the efficiency and precision of analyzing the maximum delay time of an integrated circuit. The computing method comprises: providing a circuit comprising a victim network and a plurality of aggressor networks; selecting one of a plurality of output nodes of the victim network as a representative node, and obtaining the maximum delay time of the representative node; according to the maximum delay time, obtaining initial maximum delay time of each output node except the representative node; the representative node is updated at least once, in each update, an output node is selected from the output nodes which are not used as the representative node from beginning to serve as the representative node, and the maximum delay time of the updated representative node is obtained; and according to the updated maximum delay time of the representative node, obtaining the maximum delay time of each output node which is not used as the representative node. The calculation method can be used for timing sequence verification of an integrated circuit.

The invention discloses a message delay analysis method for ARINC664 terminal traffic shaping. The method comprises the following steps: calculating an arrival curve of each message; adding the arrival curves of the messages to obtain a message frame stream aggregation arrival curve alpha w of all frameflowi in the sub virtual link queue; calculating a strict service curve beta < w > (t) of the sub-virtual link; and taking the maximum horizontal distance between the aggregation arrival curve and the strict service curve as the maximum delay of sub-virtual link traffic shaping, and taking the maximum value of the maximum delay of all sub-virtual link traffic shaping as the maximum delay of virtual link traffic shaping. The method can be used as a basis for deterministic analysis of the ARINC664 network.

The invention relates to the field of flash memory storage control, in particular to a delay monitoring device based on streaming timestamp sampling. Comprising a timestamp acquisition module which is arranged in the SSD controller and is used for acquiring a timestamp on an IO path; the delay calculation and classification module is used for calculating the collected timestamps to obtain sub-path delays; the streaming statistical unit is used for calculating average delay, maximum delay and minimum delay in real time and supporting generation of delay distribution percentile data; and the threshold value alarm and PMU linkage module is used for configuring a delay threshold value by firmware, triggering the threshold value alarm and PMU linkage module when the I / O delay exceeds the threshold value, giving an alarm and storing execution snapshots of N instructions before and after the abnormal I / O. On the premise that the area and the power consumption of the SSD controller are not obviously increased, delay monitoring with the precision of ten nanoseconds is achieved. The influence of the device on the IOPS performance is lower than 1%, and high-reliability delay diagnosis and QoS guarantee can be provided in a data center scene.

The application relates to the computer technical field and discloses a hardware consistency screening method, device, equipment and medium, which comprises the following steps: in a primary sub-cycle, fixing the phase of a data selection signal in a first double-rate synchronous dynamic random access memory (DDR); in each cycle round, selecting a delay value corresponding to each cycle round from a plurality of pre-configured delay values for a delay phase of a first data bit in the first DDR; sequentially starting and executing a continuous write command to obtain a write data code stream; after obtaining the write data code stream each time, starting and executing a continuous read command to obtain a read data code stream; then determining a minimum delay value and a maximum delay value; and then sequentially determining a first candidate delay value and a target delay value corresponding to each data bit of each DDR in the plurality of DDRs; and statistically analyzing the target delay value to determine a screening threshold. The method can improve the accuracy and reliability of data.

The present invention provides a method for video synchronization for a plurality of electronic devices, comprising the steps of: a server determining a unique delay time for each electronic device connected to the server; the server transmitting a first video playback message for displaying a first video to the plurality of electronic devices; the plurality of electronic devices determining a playback start time for the first video based on the unique delay time and a maximum delay time; and the plurality of electronic devices displaying the first video from the playback start time of the first video.

The application discloses a multi-modal scheduling method based on early exit under edge-limited equipment and relates to the field of resource offloading.The method comprises the following steps: establishing a multi-modal scheduling framework, including an edge equipment end and a server end; obtaining a plurality of early exit nodes by using an early exit mechanism; under the constraint of maximum delay, establishing a multi-modal offloading scheduling system model based on Lyapunov optimization according to network environment information and the early exit nodes, and taking Lyapunov drift penalty minimization as an optimization objective; generating a modal offloading strategy by using the multi-modal offloading scheduling system model; generating a first modal recognition result at the edge equipment end according to the modal offloading strategy, and transmitting the second spectral data to the server end after adjusting the resolution of the second spectral data, so that the server end generates a second modal recognition result; and performing probability integration on the first modal recognition result and the second modal recognition result at the edge equipment end, so as to obtain a prediction result.Compared with the prior art, the application can guarantee system stability and model processing accuracy and can improve the processing speed of the system.

A method performed by an electronic device of a wireless communication system, includes: receiving, from a first user, points of a cloud related to an application; receiving, from a plurality of mobile edge computing (MEC) servers, a plurality of computing capacities of the plurality of MEC servers; estimating a total latency of the wireless communication system, based on the points of the cloud and the plurality of computing capacities; performing a first operation of minimizing a maximum latency among a plurality of users comprising the first user, based on the total latency; performing a second operation of minimizing a number of splits of the points, based on the minimized maximum latency; performing a splitting of the points to a plurality of subsets and allocating the plurality of subsets to the plurality of MEC servers, respectively.

The application relates to an FPGA wiring method considering maximum time delay optimization, which comprises the following steps: step S1: adopting a layout optimization algorithm driven by wiring, circuit design is divided into subareas with smaller system time delay; step S2: adopting a TDM ratio initial allocation method based on a Lagrange relaxation method, optimal TDM ratio allocation results are obtained; step S3: a TDM ratio legalization algorithm based on actual constraint conditions is used to perform legalization operation on the TDM ratio allocation results; and step S4: a maximum time delay optimization algorithm based on negotiation exchange is used to further reduce the TDM ratio and reduce the system time delay. The application can effectively improve the availability of a multi-FPGA prototype system and improve wiring efficiency.

Systems and methods for verifying remote device proximity in RFID systems are described. To reduce the risk of relay attacks, a terminal may determine a distance of a remote device from the terminal. The terminal may send a computational challenge to the remote device and determine whether a latency of the response is within a maximum acceptable latency, indicating that the remote device is within a maximum acceptable distance. The maximum acceptable latency may be dynamically determined based on context information, such as a time of day, that may be correlated with a likelihood of attempted unauthorized accesses. The terminal may determine whether to perform an action associated with the remote device based on whether the response was received within the maximum acceptable latency.

Binary sparse encoding of data can be used to reduce an amount of data read from the stochastic associative memory while processing a query. Read performance of the stochastic associated memory is optimized to enhance the query throughput by modifying access patterns to reduce the time to read the stochastic associated memory. Read performance of the stochastic associative memory can be further improved through the use of cluster aware sharding and replication for parallelized similarity search. Clusters are partitioned across multiple Dual In-line Memory Modules (DIMMs), each DIMM including stochastic associative memory, to achieve maximum latency advantage.

The present disclosure provides a network entity comprising: means for providing an interface to a data network; means for receiving at least one pair of QoS flows for which the delay difference is to be monitored, and an indication of a maximum delay difference threshold for the pair of QoS flows, wherein the QoS flows are data flows having specific quality of service requirements; and means for providing monitoring, the monitoring comprising determining a delay difference for the at least one pair of QoS flows and reporting as a result of the delay difference for the pair of QoS flows exceeding a maximum delay difference threshold for the pair of QoS flows.

This invention discloses a lock-aware bounded delay preemption method and a computer-readable medium for an electronic device. Between the guest operating system and the virtual machine monitor, a shared memory control block is established for each dynamically scheduled virtual CPU, containing a lock holding count variable, a delay preemption timestamp variable, and a maximum delay threshold. The guest operating system modifies the spinlock release mechanism and initiates a virtual CPU scheduling request based on the aforementioned variables. The virtual machine monitor executes scheduling by combining the variables and the maximum delay threshold. This invention achieves precise cross-layer synchronization of virtual CPU lock holding states, allowing the virtual machine monitor to directly perceive the spinlock holding state and avoid blind preemption. Its bounded delay mechanism constrains the preemption duration without breaking the original scheduling semantics and resource allocation rules. It requires no additional hardware support or framework reconstruction, preserves the system resource scheduling logic, ensures resource utilization and stability in hybrid scheduling scenarios, and adapts to the real-time and non-real-time service deployment requirements of multi-core virtualization platforms.

The application relates to a low-latency hop-beam resource allocation method, which comprises the following steps: step 1, selecting users to be served according to a maximum delay criterion and a serial mode; step 2, considering the interference between adjacent cells, selecting a user with the maximum delay based on the user delay maximum and the serial user selection method; and step 3, balancing the delay values between different users by adopting a two-stage power allocation method to minimize the maximum delay between all users. The low-latency hop-beam resource allocation method has the following main superior technical effects: the constraint of total transmission power is fully considered in resource allocation, the maximum cumulative delay between all users in a low-orbit satellite scene is minimized under the condition of considering the inter-beam interference, and the fairness between different users is ensured.

The application discloses a high-speed master-slave type double-sampling D flip-flop with input approximation clock, comprising a control signal generating circuit, a master trigger circuit and a slave trigger circuit; the master trigger circuit and the slave trigger circuit are controlled by a clock signal CK; when the CK is at a low level, the master trigger circuit receives data input, and the slave trigger circuit is at a maintaining state; when the CK is at a high level, the master trigger circuit is at a maintaining state without being affected by the input signal, and the slave trigger circuit receives the storage state of the master trigger circuit to update the flip-flop state. Compared with the conventional D flip-flop with a scanning structure, the control of the data input signal D of the flip-flop of the application is more accurate, which is not only controlled by the clock signal, but also controlled by an enabling signal and an internal signal of the master trigger circuit; meanwhile, the slave trigger circuit receives the output signal of the master trigger circuit by using a double-sampling structure, so that the delay characteristics of the flip-flop are improved, the average delay is reduced by 8.74%, and the maximum delay is reduced by 24.9%.

Embodiments of the present application disclose a task scheduling method and device, equipment and a storage medium, comprising: in the case that a to-be-processed task is in an awake state, determining a first target global distribution queue corresponding to the to-be-processed task according to a first scheduling delay parameter corresponding to the to-be-processed task, and adding the to-be-processed task to the first target global distribution queue, wherein a second scheduling delay parameter corresponding to the first target global distribution queue matches the first scheduling delay parameter, each global distribution queue is used for mounting an unprocessed task, the first scheduling delay parameter is used for indicating a maximum delay time that can be accepted by the to-be-processed task, and the first scheduling delay parameter corresponding to a task in any global distribution queue is less than or equal to the second scheduling delay parameter corresponding to the global distribution queue to which the task belongs; and selecting a target task from the multiple global distribution queues for processing. The kernel scheduling related overhead ratio can be reduced.