Special graph avoiding method and device for optimizing manufacturability of integrated circuit

Abstract

The invention discloses a special graph avoiding method for optimizing manufacturability of an integrated circuit. The back-end process of the integrated circuit comprises five basic steps of design data input, layout planning, layout, clock tree synthesis and wiring, after the steps are completed, a generated integrated circuit layout is analyzed, a graph with the manufacturing success rate of achip manufacturer lower than a preset threshold value is found out, and it is determined that associated standard units cannot be adjacent in the specific placement direction according to the graph; and then, according to a layout graphic result extracted after the wiring of the back-end process step is completed, the formed unit limiting file is supplemented into a file list provided by a processmanufacturer in the init stage of inputting the design data, the design data is read in again, and then, the whole back-end design process is carried out again. According to the method, files related to process manufacturing provided by process manufacturers and EDA tool manufacturers do not need to be modified, and new file formats of the EDA tool manufacturers do not need to be supplemented.

Description

technical field [0001] The invention relates to the field of IC design, in particular to a special pattern avoidance method and device for optimizing the manufacturability of integrated circuits. Background technique [0002] With the rapid development of semiconductor manufacturing technology, in order to achieve faster computing speed, larger storage capacity and realize more functions, semiconductor chips are developing towards higher integration. The higher the integration of semiconductor chips, the more complicated the manufacturing process is. The current advanced integrated circuit manufacturing process generally contains hundreds of process steps. Therefore, a problem in one of the steps will cause problems in the entire semiconductor chip. , which shows that the performance of the integrated circuit fails to meet the design requirements, and in serious cases may lead to the failure of the entire chip. [0003] Therefore, it is particularly important to find out th...

AI Technical Summary

Problems solved by technology

The solution idea of ​​the present invention is to avoid the adjacency of these standard cells in certain specific directions in the back-end design of the integrated circuit. Since the process documents provided by the process manufacturer are used to solve the design rule problem of the bottom layer area of ​​the bottom standard cell, the present invention Will increase fabrication success rates on bottom standard cell area and bottom two metal layers by extending process house documentation

Images