266 results about "Chip fabrication" patented technology

The invention provides a wafer film thickness measuring method and device and chemical mechanical polishing equipment, the wafer film thickness measuring method comprises the following steps: a measuring spectrum and an interference spectrum are obtained, the measuring spectrum is formed by measuring light, and the interference spectrum is formed by reflected light after the measuring light is reflected by a wafer; calculating a correction coefficient according to the measured spectrum, and correcting the interference spectrum according to the correction coefficient; calculating a reflectivity curve of the wafer according to the corrected interference spectrum; and determining the film thickness of the wafer according to the reflectivity curve. According to the wafer film thickness measurement method, the influence of measurement noise on an interference spectrum is eliminated, the control precision of the wafer surface quality is improved, and the chip manufacturing yield is further improved.

The invention provides a crystal growth device and a crystal growth method, and solves the technical problems of low wafer utilization rate, low crystal growth speed, low efficiency, poor uniformity and the like in the existing chip manufacturing process. According to the invention, a traditional cylindrical ampoule structure is abandoned, and the annular ampoule design is innovatively adopted, so that the crystal grows into an inner hollow cylinder shape which is highly matched with the specification of a target wafer; the heater is arranged on the inner side of the ampoule, a traditional outer side heating mode is replaced, and heat is intensively acted on crystals in cooperation with an adjusting center of a heat preservation material during crystal growth, so that heat loss is reduced; the periphery of the heater is made of heat insulation materials, heat radiation leakage is effectively restrained, meanwhile, the ampoule supporting structure is adjusted, and the whole device is simple, low in cost and light in weight.

The invention provides an epitaxial wafer edge morphology compensation type wafer double-sided polishing device and method, and belongs to the technical field of semiconductor wafer ultra-precision machining. The polishing main machine comprises an upper fixed disc, a lower fixed disc and a wafer driving mechanism; the pressure loading system is used for applying adjustable pressure to the fixed disc; the polishing solution supply system is used for conveying a flow-adjustable polishing solution to the processing interface; the central control unit is in communication connection with the two systems and executes edge morphology compensation control logic, specifically, the machining pressure is adjusted in a segmented mode, and the flow of the polishing solution and the pressure are subjected to coupling change. According to the method, the atomic level flatness of the wafer surface is ensured, the edge morphology is accurately controlled, the edge thickening of the epitaxial layer is perfectly counteracted, and the photoetching yield of high-end chip manufacturing is remarkably improved.

The invention belongs to the technical field of polyurethane, and provides polyurethane resin, polyurethane gloves and a preparation method and application thereof. The polyurethane resin is prepared from the following raw materials in percentage by mass: 5%-12.5% of modified organic silicon polyol, 5%-12.5% of bio-based polyol, 5%-8% of isocyanate, 0.01%-0.02% of an antioxidant, 0.001%-0.002% of a catalyst, 1%-2% of a chain extender, 0.1%-0.7% of polyether polyol, 0.02%-0.05% of a terminating agent and 71%-75% of a solvent, the preparation raw materials of the modified organic silicon polyol comprise a dihydroxyl-terminated organic silicon prepolymer and binary acid. The polyurethane glove prepared by compounding two specific polyhydric alcohol modified organic silicon polyhydric alcohol and bio-based polyhydric alcohol as well as other substances has good wear resistance and fingerprint-free characteristic, is easy to demould, and is suitable for the field of automobile film and chip manufacturing.

The invention relates to the technical field of semiconductor manufacturing, photoetching alignment and feature recognition, and particularly discloses a photoetching alignment compensation system and method based on feature targeting. An exposed pattern on the surface of a wafer is used as a unique target reference, a built-in visual imaging structure coaxial with a photoetching light path is adopted, a sub-pixel-level feature extraction and dynamic reference real-time updating mechanism is combined, the dynamic deformation of the wafer is calculated, high-frequency compensation of a workpiece table is achieved, and nanoscale overlay precision is achieved. The core improvement of the invention lies in that a light path coaxial visual integrated structure is designed to solve the problem of external imaging parallax; a feature point self-adaptive weighted matching algorithm is provided, and the deformation compensation precision is improved; and constructing a reference map real-time micro-updating mechanism, and eliminating progressive deformation drift of the wafer. The system does not need to manufacture a special physical alignment mark, continuously verify a feature matching state in the whole exposure process and quickly trigger safety protection when the matching degree is abnormal, is suitable for a photoetching alignment process for manufacturing advanced process chips of 3nm and below, has an alignment error of less than or equal to 1.1 nm under a 12-inch wafer standard test condition, reduces the dependence on an ultra-precise workpiece table, and has a good application prospect. The system has the advantages of autonomous controllability, high interference resistance and controllable cost.

The utility model discloses a lamp chamber heat dissipation structure and photoetching equipment, and relates to the technical field of photoetching equipment. The lamp chamber heat dissipation structure comprises a light source, a lamp chamber body, an air inlet assembly and an air exhaust assembly. The air inlet assembly and the air exhaust assembly are arranged at the two opposite ends of the lamp chamber body respectively. The lamp chamber body comprises a containing cavity defined by an upper lampshade and a lower lampshade which are oppositely arranged, and the light source is arranged in the containing cavity. The air inlet assembly comprises an air inlet hole communicating with the lamp chamber body, and the lamp chamber body communicates with the outside through the air inlet hole. The exhaust assembly comprises an exhaust channel communicating with the lamp chamber body, and the lamp chamber body communicates with the outside through the exhaust channel. Air enters the lamp chamber body through the air inlet hole and then is exhausted from an outlet of the exhaust channel through the upper lampshade and the lower lampshade in sequence. According to the lamp chamber heat dissipation structure, the heat dissipation effect in the lamp chamber can be improved, and then the temperature stability of a light source and the yield of chip manufacturing are guaranteed.

The invention relates to an overlay measurement system and a measurement method, and belongs to the technical field of chip manufacturing. Interference scanning focus measurement and independent focusing imaging of double industrial cameras are combined, an overlay measurement system accurately positions focal planes of different photoetching layers on a wafer by using interference signals through one-time vertical scanning, and then the two cameras are driven to be synchronized to image plane positions of the respective focal planes, so that the alignment precision of the wafer is improved. Therefore, one-time and synchronous high-definition imaging and overlay error calculation of two layers of patterns exceeding the optical focal depth are realized, and the measurement efficiency is remarkably improved.

The invention discloses a cross-batch chip identity verification method, device and equipment, a medium and a product, and relates to the technical field of semiconductor integrated circuit testing. The method comprises the following steps: collecting multi-source entropy data in a chip manufacturing environment, and fusing the multi-source entropy data to generate an original random sequence; intercepting the original random sequence based on the identification code length to obtain a basic identification code, and performing anti-prediction encryption processing to obtain an encrypted identification code; writing the encrypted identification code into a non-fuse nonvolatile storage area of the chip, verifying the storage integrity in real time, and activating a self-destruction circuit to cope with a failure scene; and constructing a distributed index associated with a wafer batch number, a chip physical coordinate and a test timestamp, performing double collision detection in a layered manner, and when it is detected that cross-batch identification codes are repeated, freezing identification code distribution of a defective machine and generating a traceability chain. According to the scheme, the security and uniqueness of chip identity verification are improved, and the traceability of problems in the chip production and test process is enhanced.

This invention discloses an integrated integrated circuit chip structure and its fabrication method. The invention relates to the field of thermal design and thermal control technology for integrated circuit chips, addressing the problem of weak heat transfer capabilities at high heat flux density points in existing integrated circuit chips. An integrated integrated circuit chip with electrical and heat dissipation functions is fabricated on a semiconductor substrate wafer and then packaged. By combining integrated circuit fabrication technology and microfluidic fabrication technology, microfluidic channels are directly fabricated on the semiconductor substrate wafer during integrated circuit chip fabrication, rather than being fabricated separately after chip fabrication. This enables the fabrication of heat dissipation structures for multiple integrated circuit chips, reducing the cost of chip heat dissipation. A cover plate guides the cooling medium into the microfluidic channels, allowing heat from high heat flux density points on the chip to directly exchange with the cooling medium after conduction through the substrate, reducing thermal resistance during heat loss and improving heat dissipation capacity.

The invention discloses a low-water-permeability and low-oxygen-permeability photoresist protective film and a preparation method thereof, and relates to the technical field of dry film photoresist protective films, the protective film comprises an inner layer, a middle layer and an outer layer, the inner layer is prepared from 100 parts of low-density polyethylene and 0.1-0.3 part of a release agent, and the middle layer is prepared from 0.1-0.3 part of a curing agent; the middle layer is prepared from 20-80 parts of low-density polyethylene, 10-40 parts of high-density polyethylene, 10-30 parts of a binder, 6-12 parts of modified silicon dioxide and 1-2 parts of an antistatic agent, and the outer layer is prepared from 10-90 parts of low-density polyethylene, 10-40 parts of metallocene low-density polyethylene and 0.1-0.5 part of an anti-sticking agent; according to the invention, excellent water and oxygen double barrier properties are realized, excellent protection can be provided for a dry film photoresist film, the dry film photoresist film has the characteristics of high mechanical strength, static resistance, clean stripping and the like, the process stability and the product yield in chip manufacturing are powerfully guaranteed, and the application value is remarkable.

The invention belongs to the technical field of semiconductor design automation, and provides a design rule checking method for a chip layout and related equipment. The method comprises the following steps: acquiring a to-be-processed chip layout comprising at least one graphic layer; a process rule interval of a target graph layer in the chip layout and factor weights of the target graph layer on a plurality of process risk factors are obtained, the process rule interval is the minimum graph interval meeting process production, and the factor weights are used for representing the interference degree of the corresponding process risk factors on chip manufacturing; calling a conflict quantification model to calculate a conflict risk value of each adjacent graph in the target graph layer based on the process rule spacing, the factor weight and the actual spacing of each adjacent graph in the target graph layer; and based on the conflict risk value, carrying out design rule check on the target graph layer. Through the technical scheme provided by the invention, the precision of chip layout design verification can be improved.

The utility model relates to the technical field of chip manufacturing waste recovery devices, and discloses a chip manufacturing waste recovery device which comprises a box body, the inner wall of the box body is connected with a storage box in a sliding mode, the top of the storage box is connected with a turning assembly and an air drying assembly, and the outer wall of the box body is connected with a shaking assembly. Compared with the prior art, the chip manufacturing waste recovery device has the advantages that in the chip manufacturing waste recovery device, the shaking assembly is used for conveniently driving waste in the storage box to shake up and down and make close contact with cleaning liquid, stains and impurities accumulated on the surface of the waste can be cleaned away, and the cleaning effect is improved; the overturning assembly is used for conveniently overturning the waste materials stacked together in the storage box, the contact area between the waste materials and the cleaning liquid is increased, and the cleaning efficiency is improved; and the air drying assembly is used for conveniently carrying out air drying treatment on water stains on the surfaces of the waste materials after the waste materials are cleaned, and subsequent recycling treatment is facilitated.

This reduces the likelihood that devices contained in a plate-like material will be damaged and / or that chips manufactured from the plate-like material will detach from the first and / or second sheets due to the application of external force to the plate-like material. [Solution] A fastening device for fastening a second sheet to a frame unit, which includes a frame having a through hole formed therein, a first sheet whose outer edge region is fixed to the frame so as to close one end of the through hole, and a plate-like object fixed to the central region of the first sheet so as to be positioned in the through hole, wherein the fastening device comprises a holding mechanism for holding the frame unit and a fastening mechanism for fastening the second sheet to the frame unit, the holding mechanism including a holding portion for applying an attractive force to the plate-like object through the central region of the first sheet and a raised portion for raising an intermediate region of the first sheet located between the outer edge region and the central region toward or beyond the other end of the through hole.

The invention discloses a processing method, device and equipment of a superconducting quantum chip, a medium and a program product, and belongs to the field of quantum chip manufacturing. The processing method of the superconducting quantum chip can be used for improving aging caused by drifting of room temperature resistance of superconducting quantum bits in the chip after the chip is manufactured. The processing method comprises the following steps: obtaining a position parameter and a processing parameter of a superconducting quantum bit to be processed; executing a positioning operation capable of positioning the electron beam to an irradiation position associated with the position parameter of the superconducting quantum chip to be processed; and enabling the electron beam to irradiate the superconducting quantum bits according to the processing parameters. According to the scheme, the aged superconducting quantum bits can be repaired, so that the performance requirements are met, and effective quantum calculation is carried out.

A quantum-dot light conversion film, a preparation method and an application thereof and an anti-ultraviolet blue-free yellow light for chip manufacturing are provided. The preparation method includes: (1) mixing a quantum-dot concentrate with an acrylic monomer, then adding high polymer for secondary mixing, to obtain a polymer; (2) after mixing the polymer and nanoparticles, adding additives for dispersion to obtain a light conversion liquid resin; and (3) coating and curing the light conversion liquid resin to obtain a quantum-dot light conversion film. The light conversion film has high light conversion efficiency, adjustable emission peak position and narrow half peak width. Its surface forms a tightly arranged high refractive index microlens structure. When the light reaches the microlens array, as the light output surface is a lens structure and the refractive index is improved, more light is emitted in the positive direction, thereby effectively improving the light output rate.

The invention discloses an online in-situ characterization method of a chemical mechanical polishing through silicon via heterostructure, and belongs to the technical field of chip manufacturing. According to the TSV heterostructure sample, through the remarkable difference of different components of a TSV heterostructure sample matrix, an insulating layer, a barrier layer and a transmission layer in refractive index, work function and conductivity, a PiFM is taken as a core, a KPFM and a CAFM are combined, and the TSV heterostructure sample can be detected on the same platform by detecting light induction force, surface potential and current signals at a needle tip-sample position. And the real-time in-situ measurement of the TSV sample surface appearance height, roughness and interface component change is realized. According to the method, the light, electricity and force response differences between TSV heterostructure materials are fully utilized, dynamic feedback of the structure morphology and components in the CMP process is achieved, and support is provided for nano-scale and even atomic-scale polishing precision control.

The present application relates to the chip manufacturing technical field, specifically for the photonic chip multilayer overlay precision monitoring and calibration system based on image recognition, including: image acquisition module gathers super-resolution microscopic image, photoetching machine motion parameter, photoetching cavity environmental variable and overlay alignment data;Overlay alignment digital twin module constructs photoetching machine and wafer digital twin, combines chip layout and process parameters, simulates multilayer overlay deviation, exposure distortion and interlayer coupling effect through strict coupling wave analysis and rigid body kinematics algorithm;Overlay deviation intelligent analysis hub adopts YOLO-Transformer model, identifies deviation mode and locates deviation source;Visual calibration strategy generation unit constructs three-dimensional photoetching virtual scene, renders alignment and exposure process and generates calibration strategy;Self-adaptive alignment calibration unit predicts deviation trend according to calibration data, dynamically adjusts photoetching machine parameter. Thus, the problems of calibration inefficiency, insufficient precision and the like in the prior art are solved.

The invention discloses a quantum bit, a quantum chip and a quantum computer, and belongs to the technical field of quantum chip manufacturing. The quantum bit is arranged on the substrate and comprises a Josephson junction arranged on the surface of the substrate; the two through holes are adjacent to the Josephson junction, penetrate through the substrate and are used for forming a bit capacitor, and the bit capacitor and the Josephson junction jointly form the quantum bit. Through the above mode, the through hole type bit capacitor provided by the invention occupies a smaller area on the surface of the substrate, so that more quantum bits can be arranged on the limited surface of the substrate.

The application discloses an online enrichment detection system for particles and dissolved pollutants in water, which comprises a fly ash enrichment cavity, an interior of which is used for containing water, and a fly ash enrichment area between a liquid surface of the water and a top surface of the fly ash enrichment cavity; a bubble generating device arranged in the water in the fly ash enrichment cavity and used for generating bubbles for enriching particles and dissolved pollutants in the water; a gas sweeping device used for sweeping pure gas into the fly ash enrichment area and carrying away fly ash generated by the breaking of the bubbles; and a fly ash aerosol detection device used for detecting the concentration or particle size distribution of the particles in the fly ash and qualitatively and quantitatively analyzing the dissolved pollutants. The system can reliably detect low-concentration particles with a particle size of 6 nm or below in the water online, and qualitatively and quantitatively analyze the dissolved pollutants, so as to provide more accurate real-time water data for advanced chip manufacturing processes, environmental water detection, drinking water detection and industrial wastewater detection. The application further discloses an online detection method for particles and dissolved pollutants in water.

The present application relates to chip manufacturing technology field, particularly to a kind of bonding pressure disc leveling mechanism.The present application aims to provide a kind of bonding pressure disc leveling mechanism, which can control the parallelism of the upper and lower heating disc surfaces to higher precision, specifically comprising spindle, connecting fixing, connecting plate, upper heating disc and at least three leveling screws, the connecting fixing is rigid annular body, the connecting fixing is located at the bottom of the spindle periphery, the connecting plate is located below the connecting fixing, the connecting plate is connected with the lower end of the spindle, and the position of the connecting plate relative to the spindle is adjustable, each leveling screw passes through the connecting plate, the connecting fixing, connects the connecting plate with the connecting fixing, each leveling screw is arranged at intervals, the upper heating disc is located below the connecting plate, the upper heating disc is connected with the connecting plate, and the upper heating disc moves synchronously with the connecting plate.

The invention provides a method for transferring a low-dimensional semiconductor material and an array structure of the low-dimensional semiconductor material, and relates to the technical field of semiconductor material and device manufacturing. Small-area low-dimensional semiconductor materials are transferred for multiple times in a non-breakage mode to form an array, transfer of the wafer-level non-breakage low-dimensional semiconductor material array is achieved, and the wafer-level non-breakage low-dimensional semiconductor material array transfer method can be used for achieving high-yield wafer-level low-dimensional semiconductor material transfer and chip manufacturing.

The application discloses an electrostatic protection device simulation device and simulation method, comprising: establishing an electrostatic protection device model; setting a plurality of parameter values corresponding to parameters, setting a plurality of current pulse signals input into the electrostatic protection device based on different parameter values, the parameters including working temperature; inputting the parameter values into the electrostatic protection device model, applying a plurality of different current pulse signals corresponding to the parameter values to the electrostatic protection device model, respectively simulating the electrostatic protection device, and outputting voltage pulse signals; generating I-V characteristic curves corresponding to the parameter values based on the plurality of current pulse signals and the plurality of voltage pulse signals corresponding to the parameter values. The electrostatic protection effect can be verified before chip manufacturing, the simulation precision is high, the design cost of the electrostatic protection device is greatly reduced, the influence effect of the working temperature on the electrostatic protection device can be obtained, and thus the optimal working temperature of the electrostatic protection device can be obtained.

The application belongs to the technical field of radio frequency amplifiers, and specifically discloses a CMOS common-source common-gate radio frequency amplifier with temperature and process deviation compensation, which comprises a bias circuit and an amplification stage circuit; the bias circuit adopts a temperature and process deviation compensation bias circuit; when the ambient temperature changes, the bias circuit can collect the real-time temperature of an amplifying tube and generate a new bias voltage, so that the bias state of the amplification stage circuit is dynamically adjusted, and the fluctuation of the gain and power consumption of the amplifier with the temperature change is reduced; similarly, when the process parameter distribution deviation occurs in different regions of a wafer during the chip manufacturing process, the same chip bias circuit and the amplifying tube region of the amplification stage circuit are the same, the same process deviation is generated, the bias circuit can generate a new bias voltage according to the process deviation, the bias state of the amplification stage circuit is dynamically adjusted, and the fluctuation of the gain and power consumption of the amplifier with the process deviation is reduced. The application is suitable for a low-noise amplifier in a WiFi radio frequency front-end module.

1.The name of the design product: the operation graphical user interface (3) of the computer chip manufacturing practical training platform. 2.The use of the design product: running programs. 3.The design points of the design product: the interface content and interaction mode of the graphical user interface in the screen. 4.The picture or photo that best shows the design points: design 1 front view. 5.The computer is a common design, and there is no design point. The rear view, left view, right view, top view, and bottom view of designs 1 to 6 are omitted. 6.Design 1 is specified as the basic design. 7.The use of the graphical user interface: the interface is mainly used for the operation control of the chip manufacturing practical training platform. Users can personally control the platform to complete the core process steps and truly experience the whole process of chip manufacturing. 8.The human-computer interaction mode of the graphical user interface: a sliding bar is arranged at the rightmost side of the interface in design 1 front view. By clicking and dragging the purple sliding block in the sliding bar to the middle part of the sliding bar, the interface changes to design 1 interface change state diagram 1. Six device graphical option buttons of “ICP Etcher”, “PR Coater”, “Wet Stripper”, “Thermal Oxidation”, “Lithography”, and “RTP” are arranged in the interface of design 1 interface change state diagram 1. By clicking the “ICP Etcher” device graphical option button, the interface changes to design 1 interface change state diagram 2. A “next step” option button is arranged at the upper right corner of design 1 interface change state diagram 2. By clicking the “next step” option button, the interface changes to design 1 interface change state diagram 3. A “next step” option button is arranged at the upper right corner of design 1 interface change state diagram 3. After filling in the parameters in the middle part of design 1 interface change state diagram 3, by clicking the “next step” option button, the interface changes to design 1 interface change state diagram 4. The rightmost side of the design 2 main view interface is provided with a sliding bar. By clicking and dragging the purple sliding block in the sliding bar to the middle of the sliding bar, the design 2 interface change state diagram 1 is jumped to. The design 2 interface change state diagram 1 is provided with six equipment graphic option buttons, i.e. “ICP Etcher”, “PR Coater”, “Wet Stripper”, “Thermal Oxidation”, “Lithography” and “RTP” (same as design 1). By clicking the “PR Coater” equipment graphic option button, the design 2 interface change state diagram 2 is jumped to. The right upper corner of the design 2 interface change state diagram 2 is provided with a “next step” option button. By clicking the “next step” option button, the design 2 interface change state diagram 3 is jumped to. The right upper corner of the design 2 interface change state diagram 3 is provided with a “next step” option button. After filling in the parameters in the middle of the design 2 interface change state diagram 3, by clicking the “next step” option button, the design 2 interface change state diagram 4 is jumped to. The rightmost side of the design 3 main view interface is provided with a sliding bar. By clicking and dragging the purple sliding block in the sliding bar to the middle of the sliding bar, the design 3 interface change state diagram 1 is jumped to. The design 3 interface change state diagram 1 is provided with six equipment graphic option buttons, i.e. “ICP Etcher”, “PR Coater”, “Wet Stripper”, “Thermal Oxidation”, “Lithography” and “RTP” (same as design 1). By clicking the “Wet Stripper” equipment graphic option button, the design 3 interface change state diagram 2 is jumped to. The right upper corner of the design 3 interface change state diagram 2 is provided with a “next step” option button. By clicking the “next step” option button, the design 3 interface change state diagram 3 is jumped to. The right upper corner of the design 3 interface change state diagram 3 is provided with a “next step” option button. After filling in the parameters in the middle of the design 3 interface change state diagram 3, by clicking the “next step” option button, the design 3 interface change state diagram 4 is jumped to. The rightmost side of the main view interface of Design 4 is provided with a sliding bar. By clicking and dragging the purple sliding block in the sliding bar to the middle of the sliding bar, the interface changes to Design 4 interface change state diagram 1. The interface of Design 4 interface change state diagram 1 is provided with six device graphical option buttons, i.e. “ICP Etcher”, “PR Coater”, “Wet Stripper”, “Thermal Oxidation”, “Lithography” and “RTP” (the same as Design 1). By clicking the “Thermal Oxidation” device graphical option button, the interface changes to Design 4 interface change state diagram 2. The upper right corner of Design 4 interface change state diagram 2 is provided with a “next step” option button. By clicking the “next step” option button, the interface changes to Design 4 interface change state diagram 3. The upper right corner of Design 4 interface change state diagram 3 is provided with a “next step” option button. After filling in the parameters in the middle of Design 4 interface change state diagram 3, by clicking the “next step” option button, the interface changes to Design 4 interface change state diagram 4. The rightmost side of the main view interface of Design 5 is provided with a sliding bar. By clicking and dragging the purple sliding block in the sliding bar to the middle of the sliding bar, the interface changes to Design 5 interface change state diagram 1. The interface of Design 5 interface change state diagram 1 is provided with six device graphical option buttons, i.e. “ICP Etcher”, “PR Coater”, “Wet Stripper”, “Thermal Oxidation”, “Lithography” and “RTP” (the same as Design 1). By clicking the “Lithography” device graphical option button, the interface changes to Design 5 interface change state diagram 2. The upper right corner of Design 5 interface change state diagram 2 is provided with a “next step” option button. By clicking the “next step” option button, the interface changes to Design 5 interface change state diagram 3. The upper right corner of Design 5 interface change state diagram 3 is provided with a “next step” option button. After filling in the parameters in the middle of Design 5 interface change state diagram 3, by clicking the “next step” option button, the interface changes to Design 5 interface change state diagram 4. The rightmost side of the design 6 main view interface is provided with a sliding bar. By clicking and dragging the purple sliding block in the sliding bar to the middle of the sliding bar, the design 6 interface change state diagram 1 is jumped to. The design 6 interface change state diagram 1 is provided with six equipment graphic option buttons (the same as the design 1) of “ICP Etcher”, “PR Coater”, “Wet Stripper”, “Thermal Oxidation”, “Lithography” and “RTP”. By clicking the “RTP” equipment graphic option button, the design 6 interface change state diagram 2 is jumped to. The right upper corner of the design 6 interface change state diagram 2 is provided with a “next step” option button. By clicking the “next step” option button, the design 6 interface change state diagram 3 is jumped to. The right upper corner of the design 6 interface change state diagram 3 is provided with a “next step” option button. After filling in the parameters in the middle of the design 6 interface change state diagram 3, the “next step” option button is clicked, and the design 6 interface change state diagram 4 is jumped to.

The utility model relates to the technical field of biochip manufacturing equipment, in particular to a membrane uncovering mechanism for a membrane, which comprises a working table, a sliding frame and a clamping jaw assembly, the working table is provided with a waste material port, the sliding frame is horizontally and slidably mounted on the working table through a sliding component, and the clamping jaw assembly is arranged on the working table. The clamping jaw assembly is installed on the sliding frame in a lifting mode through a lifting assembly, a clamping jaw used for uncovering a film is arranged below the clamping jaw assembly, and after the film is uncovered, the clamping jaw horizontally slides and moves to the waste material opening through the sliding frame to discard the PDMS layer. According to the film uncovering mechanism, through cooperation of the sliding assembly, the lifting assembly, the clamping jaw assembly and the like, automatic operation of the film uncovering process can be achieved, the film uncovering efficiency is improved, and damage to the substrate is avoided.

The invention relates to the technical field of plant molecular markers, in particular to a millet whole genome 65K liquid chip and application thereof.The millet whole genome 65K liquid chip is obtained through the following steps that re-sequencing data of a millet material is obtained, and then the re-sequencing data is subjected to quality control, mapping with a reference genome and identification and screening of variation sites; according to the indexes of the variation sites, combining the positions of the sites on the chromosomes, analyzing upstream and downstream sequences of the variation sites, and selecting the variation sites which can be used for chip development; the obtained variation site and 50bp sequences before and after the variation site are used, and an Infinium chip manufacturing technology is used for manufacturing the millet whole genome 65K liquid phase chip; based on high-depth whole genome re-sequencing data of large-scale millet germplasm materials, the millet whole genome 65K liquid chip is successfully developed, and can be widely applied to the fields of millet genotype detection, variety identification, genetic positioning, genetic diversity analysis, whole genome correlation analysis, whole genome selective breeding and the like. And important technical support is provided for molecular breeding development of millet.

The invention discloses a quantum device, a quantum chip and a quantum computer, and belongs to the technical field of quantum chip manufacturing. The quantum device comprises a substrate of which the surface is provided with quantum bits; the resonant cavity and the quantum bit are arranged on the substrate in a coplanar mode, and the resonant cavity is coupled with the quantum bit and used for reading the quantum state of the quantum bit; wherein the resonant cavity takes the quantum bit as a starting point and spirally extends in a direction far away from the starting point. Through the mode, the quantum device provided by the invention comprises the spiral resonant cavity, and the resonant cavity in the form is smaller in size, namely, the area occupied by the surface of the substrate is smaller, so that more quantum devices such as quantum bits can be integrated on the surface of the substrate with the same size.

The utility model provides a kind of EUV super high light-gathering efficiency reflector bowl combination device, including base (1), the base (1) is provided with main reflector bowl (6), side reflector ring bowl (7) and lower reflector bowl (8);It is characterized by: the lower reflector bowl (8) is fixedly supported by support mechanism (3) on side reflector ring bowl (7), and the lower reflector bowl (8) is scattered to the side reflector ring bowl (7) on the EUV (11) of plasma emission again reflection and the reflection EUV light of main reflector bowl (6) superposition converges on same intermediate focus (4).The utility model improves 30-45% of intermediate focus (4) light power by the focusing of lower reflector bowl (8) and side reflector ring bowl (7) structure, greatly saves electric energy, and makes chip manufacturing more environmentally friendly.

A chip manufacturing method and apparatus. The chip manufacturing method includes: fabricating a plurality of predetermined chip sets on a wafer, wherein each predetermined chip set includes a plurality of individual chips; performing a conformity test on each individual chip in the plurality of predetermined chip sets; and dicing the wafer based on the test results, wherein, in response to each chip in a first predetermined chip set being conformable, the first predetermined chip set is diced as a whole, or in response to a portion of chips in a second predetermined chip set being conformable, the conformable and non-conforming individual chips in the second predetermined chip set are diced and separated. This chip manufacturing method dices the wafer in different ways based on the conformity of the individual chips formed on the wafer, thereby reducing manufacturing costs.

The invention relates to the technical field of LED chip manufacturing, in particular to a Mini red light emitting diode and a preparation method thereof. After an epitaxial structure is grown through an MOCVD method, a substrate is replaced through bonding, a table top and an ISO isolation channel are prepared through etching, an Al2O3 protective layer and an SiO2 auxiliary protective layer are deposited in sequence, two sets of laminated DBR reflecting layers are evaporated, an Al-free electrode bonding pad is manufactured on the ISO isolation channel through etching, and the Mini red light emitting diode is obtained. The Mini red light emitting diode electrode prepared by the preparation method has good coverage of each layer, can effectively block water vapor erosion, fundamentally improves the electrochemical stability of the electrode by optimizing the laminated metal structure design of the electrode, avoids migration failure of the electrode, guarantees the stable photoelectric performance of the device in 72 hours in a harsh environment, and improves the reliability of the device. And the reliability and the light emitting efficiency of outdoor inverted application are greatly improved.