620 results about "Chip fabrication" patented technology

The invention discloses a chip surface defect visual detection method and system, and the method comprises the steps: carrying out the high-sensitivity imaging through the dynamic adaptation of a quantum imaging enhancement module to the surface reflectivity, and achieving the sparse efficient processing of a defect signal through the combination of event-driven vision and a pulse neural network; based on a risk thermodynamic diagram generated in real time, intelligently scheduling detection precision and speed resources, and utilizing multi-modal feature decoupling and a federal knowledge graph to accurately associate defects and process roots; the digital twinning module synchronously predicts a defect evolution path and drives online adjustment and optimization of process parameters, and meanwhile the dynamic compensation module corrects optical defocus in real time. According to the invention, full-detection coverage of nanoscale defects is realized, a defect transfer chain is actively blocked while the detection efficiency is improved, and the chip manufacturing yield and reliability are remarkably improved.

The invention relates to the technical field of RFID chip manufacturing, in particular to an RFID chip image anomaly detection method and system based on intelligent learning. The method comprises the following steps: acquiring a real-time RFID chip sampling image set, performing feature alignment based on a registration template, generating an average grey-scale map by using an alignment image set, and obtaining a chip edge mask image set by using an edge search algorithm; segmenting the edge mask image set of the RFID chip to obtain an effective edge mask variance image set of the RFID chip; integrating the variance image set to obtain a pre-generated variance image; acquiring field environment data of the RFID chip and performing sensitivity coefficient estimation to obtain an edge sensitivity coefficient; and performing convolution filtering smoothing processing on the pre-generated variance image to obtain a chip edge variance image, and constructing an RFID chip image anomaly detection model based on the edge variance image and the average grey-scale image. According to the invention, the detection accuracy and stability are improved.

The invention discloses a vacuum microcavity interferometer chip, a manufacturing method and a low-drift optical pressure sensor, a film island structure is formed on the upper surface of a first substrate, and the film island structure comprises a protruding part and a pressure sensitive film surrounding the protruding part; a first side wall part, a getter cavity, a second side wall part and an F-P interference cavity located in the center are sequentially arranged on the lower surface of the first substrate in the radial direction, a first reflecting surface is deposited on the lower surface of the first substrate in the F-P interference cavity, and a second reflecting surface is deposited on the upper surface of the second substrate in the F-P interference cavity. A first optical antireflection film is deposited on the surface of the protruding part, and the first optical antireflection film, the protruding part, the pressure sensitive film, the first reflecting surface and the second reflecting surface have the same center; the filter further comprises a vent hole, and the vent hole is formed in the second side wall part and used for communicating the getter cavity and the F-P interference cavity.

The invention discloses a wafer placement state detection method in a wafer box and a wafer state detection system, and relates to the technical field of chip manufacturing, the wafer box comprises a box body, one end of the box body in a first direction is open, the box body is provided with a plurality of slots at intervals along a second direction, and the slots are inserted into the slots. The plurality of slots are provided with sockets facing the open end of the box body, so that a plurality of wafers can be correspondingly inserted and installed, a wafer state detection system is arranged on the wafer box, and the wafer state detection system comprises at least one signal transceiver and a controller in telecommunication connection with the signal transceiver; the method for detecting the placement state of the wafer in the wafer box comprises the following steps: after the wafer is inserted into the slot and the signal transceiver is located at a set detection position, controlling the signal transceiver to send out a detection signal; and obtaining a return signal received by the signal transceiver, and determining whether the placement state of the wafer is correct or not according to the return signal. The invention aims to realize automatic detection of the state of the wafer in the wafer box.

The invention discloses a copper wire bonding process for a silicon carbide power device chip after copperization, and relates to the technical field of chip manufacturing, and the copper wire bonding process comprises the following specific steps: step 1, chip pretreatment: preparing the silicon carbide power device chip, placing the chip in a cleaning tank, and cleaning the silicon carbide power device chip; the method has the advantages that the nickel layer, the metal palladium layer and the metal copper layer with the specific thickness and sequence are evaporated on the surface of the chip, the buffer layer with the gradient structure is prepared, the plating uniformity and the appropriate thickness are ensured through the accurately-controlled electrode layer evaporation process, the problems of wafer warping, buffer failure and the like are solved, and the production efficiency is improved. A stable electrical connection basis is provided for the chip, the elasticity modulus of the gradient structure of the buffer layer can be gradually reduced from contact with the electrode layer to contact with the copper wire according to the stress distribution characteristics, the stress dispersion effect is greatly improved, the reliability of the chip in the bonding and subsequent use processes is remarkably improved, the service life of the chip is prolonged, and the production cost is reduced. And the risk of product failure caused by chip damage is reduced.

The invention provides a federated learning-based chip manufacturing process parameter optimization method and system, and relates to the technical field of chips, and the method comprises the steps: collecting multi-factory process parameters and yield data, screening key parameters through wavelet transform and dual evaluation, and constructing a deep Q network model; ethnic group division is carried out based on process trajectory similarity, differential privacy and homomorphic encryption are adopted to protect data security, and ethnic group optimization is realized through an attention mechanism and knowledge distillation; and setting a third-level time window monitoring yield, and dynamically adjusting an optimization strategy. According to the method, the chip manufacturing yield can be effectively improved, data privacy is protected, and intelligent optimization of process parameters is realized.

The invention provides an optical proximity effect correction method and system, a terminal and a medium, and the method comprises the steps: obtaining a plurality of initial parameter combinations of a photoetching mask design pattern, so as to form an initial population; wherein each initial individual in the initial population corresponds to a group of initial parameter combinations; determining a plurality of optimization indexes of the photoetching mask design graph, and determining an optical proximity effect correction function based on the plurality of optimization indexes and constraint conditions; and based on the optical proximity effect correction function, obtaining an optimal parameter combination of the photoetching mask design pattern in the iteration process of the initial population. According to the invention, the optimization algorithm is innovatively introduced into the field of optical proximity effect correction, comprehensive optical proximity effect correction is realized by introducing a plurality of optimization indexes, the manufacturing requirement of a high-precision silicon optical chip is effectively met, and the performance of the silicon optical chip is effectively improved.

The invention provides a wafer film thickness measuring method and device and chemical mechanical polishing equipment, the wafer film thickness measuring method comprises the following steps: a measuring spectrum and an interference spectrum are obtained, the measuring spectrum is formed by measuring light, and the interference spectrum is formed by reflected light after the measuring light is reflected by a wafer; calculating a correction coefficient according to the measured spectrum, and correcting the interference spectrum according to the correction coefficient; calculating a reflectivity curve of the wafer according to the corrected interference spectrum; and determining the film thickness of the wafer according to the reflectivity curve. According to the wafer film thickness measurement method, the influence of measurement noise on an interference spectrum is eliminated, the control precision of the wafer surface quality is improved, and the chip manufacturing yield is further improved.

The invention provides a crystal growth device and a crystal growth method, and solves the technical problems of low wafer utilization rate, low crystal growth speed, low efficiency, poor uniformity and the like in the existing chip manufacturing process. According to the invention, a traditional cylindrical ampoule structure is abandoned, and the annular ampoule design is innovatively adopted, so that the crystal grows into an inner hollow cylinder shape which is highly matched with the specification of a target wafer; the heater is arranged on the inner side of the ampoule, a traditional outer side heating mode is replaced, and heat is intensively acted on crystals in cooperation with an adjusting center of a heat preservation material during crystal growth, so that heat loss is reduced; the periphery of the heater is made of heat insulation materials, heat radiation leakage is effectively restrained, meanwhile, the ampoule supporting structure is adjusted, and the whole device is simple, low in cost and light in weight.

The invention provides an epitaxial wafer edge morphology compensation type wafer double-sided polishing device and method, and belongs to the technical field of semiconductor wafer ultra-precision machining. The polishing main machine comprises an upper fixed disc, a lower fixed disc and a wafer driving mechanism; the pressure loading system is used for applying adjustable pressure to the fixed disc; the polishing solution supply system is used for conveying a flow-adjustable polishing solution to the processing interface; the central control unit is in communication connection with the two systems and executes edge morphology compensation control logic, specifically, the machining pressure is adjusted in a segmented mode, and the flow of the polishing solution and the pressure are subjected to coupling change. According to the method, the atomic level flatness of the wafer surface is ensured, the edge morphology is accurately controlled, the edge thickening of the epitaxial layer is perfectly counteracted, and the photoetching yield of high-end chip manufacturing is remarkably improved.

The invention relates to a vacuum microcavity interferometer chip, a manufacturing method and a wide-range optical pressure sensor. Comprising a first substrate and a second substrate, the second substrate and the first substrate are bonded into a whole, a pressure sensitive film is manufactured on the first substrate, a first reflecting surface is deposited on the pressure sensitive film, and a second reflecting surface corresponding to the first reflecting surface is deposited on the second substrate. After the two substrates are bonded, the first reflecting surface and the second reflecting surface form an F-P optical interference cavity, at least one getter cavity is arranged on the first substrate and / or the second substrate, a getter film is arranged on the surface of the getter cavity, and the getter cavity and the F-P optical interference cavity are separated and connected through an air channel, so that the size of the air channel can be made to be very small, and the size of the getter cavity is smaller than that of the F-P optical interference cavity. A small amount of particles generated after the getter is activated are prevented from polluting an optical film to cause device failure; the whole sensor is of a sealed structure and is not provided with a structure externally connected with the chip, so that the overall airtightness of the chip is ensured, and the vacuum degree requirement of subsequent shell packaging is reduced.

The invention relates to the technical field of integrated circuit manufacturing, in particular to a wafer-level multi-chip metal wiring method and a wafer. Metal wires are arranged in a layered mode, and preset intervals are set for isolation; jumper connection between the metal wires of different metal layers is achieved through the through holes at the intersections of the scribing grooves, high-density signal transmission is achieved through the multiple layers of metal wires, and the situation that two adjacent metal wires are short-circuited together due to cutting extrusion during scribing can be prevented through cross-layer jumpers and interval isolation arrangement of the metal wires. By means of the layered metal wiring structure and spaced wiring, efficient data burning of thousands of chips on the wafer is achieved, stray capacitance and short circuit risks are remarkably reduced, meanwhile, the wafer utilization rate and burning efficiency are improved, the number and grouping mode of the chip arrays can be flexibly adjusted according to requirements, and the method is suitable for large-scale popularization and application. And the manufacturing requirements of chips with different scales are met.

The invention relates to a yov10-fused chip multi-dimensional quality inspection device and method, and the device comprises a hardware quality inspection module which is used for obtaining the surface reflection light field data of a chip through dynamic light field regulation and control, and carrying out the defect detection based on the light field analysis; the software quality inspection module is configured with a cascade architecture of a lightweight network and an improved YOLOv10 detection network, the first-stage lightweight network performs defect existence judgment on the data of which the defects are not detected by the hardware quality inspection module, and the second-stage improved YOLOv10 network performs multi-scale positioning and morphological quantitative analysis on the judged defect data; and the quality inspection execution mechanism is used for implementing differentiated sorting strategies based on quality inspection results of the hardware quality inspection module and the software quality inspection module. According to the technical closed loop formed by the three parts, the chip quality inspection link is upgraded from single visual inspection to multi-dimensional intelligent interpretation and from manual sorting to full-automatic closed loop processing, and efficient and reliable quality control guarantee is provided for the chip manufacturing industry.

The invention relates to the technical field of chip manufacturing, and provides a semiconductor wafer trimming device and method.A wafer placed on a pre-calibration workbench is calibrated through a calibration arm assembly, so that the wafer is adjusted to the center of the pre-calibration workbench; and after calibration, the calibration arm assembly is controlled to clamp the edge of the wafer and move the edge of the wafer to the center of the trimming working disc along the Y-axis direction, so that the problem that the wafer trimming equipment is inconvenient to calibrate after being placed due to the use of a hollow working suction disc is solved, and the calibration arm can well protect products with size deviation; according to the calibration device, damage in the calibration process is avoided, the calibration structure is simple, the calibration device only needs to be conveyed to the trimming working disc in the Y-axis direction after calibration, the position deviation in the X-axis direction does not need to be considered, the hundred-micron-level calibration precision is achieved, and the efficiency of the whole calibration process is high; and meanwhile, the edge of the wafer is clamped and carried, so that a traditional vacuum adsorption mode is changed, and pollution caused by dust in a vacuum air path is reduced.

The invention discloses a Micro-LED chip array integrated with a homogeneous micro-lens array and a preparation method thereof, and the method comprises the steps: carrying out the wafer-level precise bonding of a Micro-LED light-emitting pixel array and a CMOS drive circuit substrate, removing a substrate, integrating a homogeneous pixel-level GaN micro-lens array on a GaN-based pixel array through the photoetching, hot melting backflow and dry etching technologies, and carrying out the precise bonding of the micro-LED light-emitting pixel array and the CMOS drive circuit substrate. And finally, realizing the full-pixel common cathode conduction of the Micro-LED chip by adopting a metal interconnection process. According to the method, the Micro-LED pixel array and the micro-lens array are homogeneously integrated, are made of the same material and have no refractive index difference, so that no Fresnel loss exists on an interface, and the light extraction efficiency of a chip is improved. In addition, the method is simple in manufacturing process, low in cost, good in chip structure reliability, high in stability and suitable for being applied to industrial chip manufacturing.

The invention relates to an MEMS (Micro Electro Mechanical System) packaging method. The method comprises the following steps of S1, bonding a device layer wafer on a substrate; s2, etching the device layer wafer to obtain an acceleration sensor structure and a gyroscope structure; s3, in a nitrogen atmosphere, pre-bonding an upper cover plate on the acceleration sensor structure and the gyroscope structure, so that an acceleration sensor structure cavity and a gyroscope structure cavity between the upper cover plate and the substrate are filled with nitrogen; and S4, eliminating nitrogen in the cavity of the gyroscope structure, and bonding the acceleration sensor structure and the gyroscope structure on the upper cover plate to obtain the gyroscope structure vacuum chamber. The acceleration sensor chip and the gyroscope chip are prepared on one substrate through MEMS packaging, the preparation process is shortened, the manufacturing period and cost of the MEMS chips are reduced, combined packaging of the two chips is achieved through combined nesting of different types of MEMS packaging modes, and the packaging efficiency is improved. The packaging volume is reduced, and the space utilization rate and the integration capability are improved.

The invention provides a multi-overlay alignment method for a sensing chip projection photoetching machine, which belongs to the field of photoetching and comprises a primary overlay alignment algorithm and a secondary overlay alignment algorithm. The primary overlay alignment algorithm calculates the position coordinates of the diaphragm in the image and the deviation values in the X direction and the Y direction by recognizing the outer contour of the diaphragm, and is used for determining the position of the diaphragm through primary exposure. And the secondary overlay alignment algorithm is used for accurately calculating the center coordinate of the diaphragm and the deviation values of the X direction, the Y direction and the rotation angle (R direction) by identifying the left and right positioning marks in the pattern aiming at the diaphragm with a layer of pattern. Through the deviation values, the air bearing table, the workpiece table and the mask table of the photoetching machine can be compensated in real time, so that accurate exposure of the diaphragm is ensured. According to the alignment method disclosed by the invention, the alignment precision of each layer of pattern in the manufacturing process of the sensing chip is remarkably improved, and defects caused by alignment errors are reduced.

The invention belongs to the technical field of manufacturing of Mini-LED chips, and discloses a plane stretching type Mini-LED chip film expanding device and method capable of correcting errors. A plane stretching type chip film expanding device capable of correcting errors comprises a first film expanding mechanism, a second film expanding mechanism, a film pressing frame, a scanning camera and an error correcting mechanism. A first film expanding mechanism and a second film expanding mechanism are adopted for integrally stretching a blue film, then a scanning camera detects the position of a chip on the blue film, a correction disc is adsorbed through an adsorption through hole to locally fix the part, without deviation, of the chip in the blue film, and then the part, with deviation and without fixation, of the chip in the blue film is jacked up through a marble; the blue film is locally expanded, so that the position of the chip on the blue film is corrected, the position of the chip is accurately adjusted, and the problems that a conventional film expanding device cannot randomly adjust the local stretching amount of the blue film and cannot correct the position deviation of the local chip are solved.

The invention provides a chip testing method based on an ATE platform, and relates to the technical field of chip manufacturing and testing. According to the method, multiple advanced test technologies and intelligent algorithms are creatively integrated, test environment parameters are accurately controlled through an intelligent environment regulation and control system, radio frequency and digital signals are efficiently processed in cooperation with a test engine, a test execution stream optimizes a high-speed interface test by using a chip built-in Loopback function and an adaptive algorithm, and the test efficiency is improved. The intelligent control and analysis system dynamically adjusts a test process and accurately predicts chip defects based on a federal learning framework, and realizes Chiplet interconnection verification and closed-loop data analysis feedback optimization of a test program at the same time. The chip testing efficiency and precision are effectively improved, the testing cost is reduced, dependence on expensive equipment is reduced, the method can be widely applied to various chip testing scenes, and remarkable economic benefits and technical advantages are brought to chip manufacturing enterprises.

The invention belongs to the technical field of laser marking, and particularly relates to an automatic PCB marking device for chip manufacturing, the automatic PCB marking device comprises a belt conveyor, an automatic laser marking machine and a grabbing mechanism, the automatic laser marking machine is fixed at the discharging end of the belt conveyor, the grabbing mechanism is arranged at the feeding end of the belt conveyor, a mounting frame is further fixed on the belt conveyor, and the mounting frame is connected with the automatic laser marking machine. A thickness detection module and a controller are fixed to the inner wall of the top of the mounting frame, a feeding table is arranged on one side of the feeding end of the belt conveyor, a qualified product discharging table and a defective product discharging table are arranged on the other side of the feeding end of the belt conveyor, and an image detection system is mounted in the automatic laser marking machine. According to the method, the copper foil thickness of the PCB is detected before marking, and the power of the marking machine is accurately calculated and adjusted according to the established mathematical model, so that the problems of unclear marking, overburning or light mark and the like caused by the thickness difference of the copper foil can be effectively avoided, and the stability and consistency of the marking quality are ensured.

The utility model discloses a spot check machine for chip manufacturing, comprising a workbench, the top of the workbench is fixedly provided with an overturning assembly, the overturning assembly comprises a double-shaft cylinder and a moving frame, the double-shaft cylinder is fixedly installed on one side of the workbench, the moving frame is fixedly connected with the output end of the double-shaft cylinder, and the moving frame is fixedly connected with the output end of the double-shaft cylinder. An electric push rod is fixedly installed at the top of the movable frame, the output end of the electric push rod is fixedly connected with a toothed plate, one side of the movable frame is connected with a rotating shaft through a bearing, the side wall of the rotating shaft is fixedly connected with a first gear, and the first gear is connected with the toothed plate in a meshed mode. According to the sampling inspection machine for chip manufacturing, through the arranged overturning assembly, a chip can be overturned, so that the two faces of the chip can be detected, no omission exists in the detection process, the detection effect cannot be affected by omission, and the quality of a chip product is higher.

The invention relates to a vacuum microcavity interferometer chip, a manufacturing method and an ultra-high precision optical pressure sensor, the lower surface of a first substrate is etched to form a concave cavity, after the first substrate and a second substrate are bonded, the concave cavity forms an F-P interference cavity, and the F-P interference cavity forms an F-P cavity; a first reflecting surface is arranged on the surface of the first substrate in the F-P interference cavity, a second reflecting surface is arranged on the surface of the second substrate in the F-P interference cavity, an annular cavity is formed in the upper surface of the third substrate, and the getter film is deposited on at least one surface in the annular cavity. The second substrate is provided with at least one vent hole, and the vent hole is communicated with the F-P interference cavity and the annular cavity; the projections of the annular cavity and the F-P interference cavity on the horizontal plane at least partially coincide.

The invention belongs to the technical field of polyurethane, and provides polyurethane resin, polyurethane gloves and a preparation method and application thereof. The polyurethane resin is prepared from the following raw materials in percentage by mass: 5%-12.5% of modified organic silicon polyol, 5%-12.5% of bio-based polyol, 5%-8% of isocyanate, 0.01%-0.02% of an antioxidant, 0.001%-0.002% of a catalyst, 1%-2% of a chain extender, 0.1%-0.7% of polyether polyol, 0.02%-0.05% of a terminating agent and 71%-75% of a solvent, the preparation raw materials of the modified organic silicon polyol comprise a dihydroxyl-terminated organic silicon prepolymer and binary acid. The polyurethane glove prepared by compounding two specific polyhydric alcohol modified organic silicon polyhydric alcohol and bio-based polyhydric alcohol as well as other substances has good wear resistance and fingerprint-free characteristic, is easy to demould, and is suitable for the field of automobile film and chip manufacturing.

The invention relates to the technical field of semiconductor manufacturing, photoetching alignment and feature recognition, and particularly discloses a photoetching alignment compensation system and method based on feature targeting. An exposed pattern on the surface of a wafer is used as a unique target reference, a built-in visual imaging structure coaxial with a photoetching light path is adopted, a sub-pixel-level feature extraction and dynamic reference real-time updating mechanism is combined, the dynamic deformation of the wafer is calculated, high-frequency compensation of a workpiece table is achieved, and nanoscale overlay precision is achieved. The core improvement of the invention lies in that a light path coaxial visual integrated structure is designed to solve the problem of external imaging parallax; a feature point self-adaptive weighted matching algorithm is provided, and the deformation compensation precision is improved; and constructing a reference map real-time micro-updating mechanism, and eliminating progressive deformation drift of the wafer. The system does not need to manufacture a special physical alignment mark, continuously verify a feature matching state in the whole exposure process and quickly trigger safety protection when the matching degree is abnormal, is suitable for a photoetching alignment process for manufacturing advanced process chips of 3nm and below, has an alignment error of less than or equal to 1.1 nm under a 12-inch wafer standard test condition, reduces the dependence on an ultra-precise workpiece table, and has a good application prospect. The system has the advantages of autonomous controllability, high interference resistance and controllable cost.

The utility model discloses a lamp chamber heat dissipation structure and photoetching equipment, and relates to the technical field of photoetching equipment. The lamp chamber heat dissipation structure comprises a light source, a lamp chamber body, an air inlet assembly and an air exhaust assembly. The air inlet assembly and the air exhaust assembly are arranged at the two opposite ends of the lamp chamber body respectively. The lamp chamber body comprises a containing cavity defined by an upper lampshade and a lower lampshade which are oppositely arranged, and the light source is arranged in the containing cavity. The air inlet assembly comprises an air inlet hole communicating with the lamp chamber body, and the lamp chamber body communicates with the outside through the air inlet hole. The exhaust assembly comprises an exhaust channel communicating with the lamp chamber body, and the lamp chamber body communicates with the outside through the exhaust channel. Air enters the lamp chamber body through the air inlet hole and then is exhausted from an outlet of the exhaust channel through the upper lampshade and the lower lampshade in sequence. According to the lamp chamber heat dissipation structure, the heat dissipation effect in the lamp chamber can be improved, and then the temperature stability of a light source and the yield of chip manufacturing are guaranteed.

The invention discloses an overlay mark center positioning method and a related device, and relates to the technical field of chip manufacturing, and the method comprises the steps: determining an approximate position of an overlay mark through employing a preset region of interest, carrying out the gray projection of an overlay mark image in a horizontal direction and a vertical direction in the preset region of interest, generating a one-dimensional gray curve, and carrying out the positioning of the center of the overlay mark. Two-dimensional information of an overlay mark image is reduced to one-dimensional information, the calculation data volume is effectively reduced, then a target curve is obtained by performing noise reduction processing on a one-dimensional gray curve, noise interference is reduced, accuracy and effectiveness of overlay mark center positioning are guaranteed, and finally, the overlay mark center positioning accuracy and effectiveness are improved by utilizing the priori knowledge that the overlay mark is symmetrical in the horizontal direction and the vertical direction. And calculating the symmetric length of each point in the target search range of the target curve to obtain a symmetric curve formed by the symmetric lengths of the points, and determining the peak value of the symmetric curve as the overlay mark center to ensure the accuracy and reliability of the overlay mark center.

The invention relates to an overlay measurement system and a measurement method, and belongs to the technical field of chip manufacturing. Interference scanning focus measurement and independent focusing imaging of double industrial cameras are combined, an overlay measurement system accurately positions focal planes of different photoetching layers on a wafer by using interference signals through one-time vertical scanning, and then the two cameras are driven to be synchronized to image plane positions of the respective focal planes, so that the alignment precision of the wafer is improved. Therefore, one-time and synchronous high-definition imaging and overlay error calculation of two layers of patterns exceeding the optical focal depth are realized, and the measurement efficiency is remarkably improved.

The invention discloses a wafer detection data analysis method, device and equipment, a medium and a product, and is applied to the technical field of chip manufacturing. According to the method, a detection data picture comprising a plurality of crystal grains is displayed, so that a related user can conveniently divide a plurality of corresponding target areas in the detection data picture according to requirements; and performing data analysis on the detection data picture based on each target area. Therefore, according to the technical scheme, the detection data generated by actual production can be flexibly classified by freely dividing the areas, so that the requirement of accurate data analysis is met. By means of free selection of a user, region division can be closer to facts, detection data of different distribution modes can be visually checked and analyzed, grain distribution can be rapidly tracked and analyzed, convenience is brought to data analysis of uneven distribution or special distribution modes, and the grain distribution rule in a detection data picture is effectively judged.

The invention provides an SIC chip and a manufacturing method thereof, and belongs to the field of semiconductors. The manufacturing method of the SIC chip comprises the steps that the SIC chip is provided, passivation layers are deposited on the inner wall and the bottom of a through hole, and the passivation layers extend to a metal covering layer around the through hole; forming a first PI layer on the surface of the passivation layer, and filling the through hole; a second PI layer is formed on the surface of the first PI layer, and the first PI layer and the second PI layer are opposite in adhesive property; and forming a plastic package layer on the surface of the second PI layer, wherein the plastic package layer covers the second PI layer and the metal covering layer. According to the invention, two PI layers with opposite colloidality are formed. By using the two PI layers, the surface stress gradient structure of the SIC chip can be formed, and the shear stress between the molding compound and the SIC chip in the thermal cycle process can be effectively reduced, so that the shear stress at the edge and the corner of the SIC chip can be reduced, the layering of the SIC chip and the molding compound and the cracking of the SIC chip can be avoided, and the service life of the SIC chip is prolonged. And physical property abnormity and electrical property failure of the device can be further avoided.

The utility model discloses an integrated circuit chip storage device, and relates to the technical field of chip manufacturing. The device comprises a storage seat, a cylinder body, an ejection mechanism and a cover plate, a circular groove is formed in the top of the storage seat, the cylinder is rotationally arranged in the circular groove, a plurality of stepped storage grooves which are uniformly distributed along the circumference are formed in the top of the cylinder, and the stepped storage grooves are used for placing integrated circuit chips; an ejection hole is formed in the bottom surface of each stepped storage groove, and the ejection mechanism is arranged in an inner cavity of the storage seat and comprises an ejection rod and a pressing rod; the ejector rod is located under the ejector hole and is in clearance fit with the ejector hole, and the pressing rod is located in a groove in the front face of the storage base. According to the integrated circuit chip storage device, the cylinder body and the ejection mechanism are arranged, and the integrated circuit chips in the stepped storage grooves can be ejected through the ejection mechanism, so that the integrated circuit chips are conveniently taken out, and the problem that the integrated circuit chips of an existing storage device are not convenient to take out is solved.