378 results about "Chip fabrication" patented technology

The invention discloses a chip surface defect visual detection method and system, and the method comprises the steps: carrying out the high-sensitivity imaging through the dynamic adaptation of a quantum imaging enhancement module to the surface reflectivity, and achieving the sparse efficient processing of a defect signal through the combination of event-driven vision and a pulse neural network; based on a risk thermodynamic diagram generated in real time, intelligently scheduling detection precision and speed resources, and utilizing multi-modal feature decoupling and a federal knowledge graph to accurately associate defects and process roots; the digital twinning module synchronously predicts a defect evolution path and drives online adjustment and optimization of process parameters, and meanwhile the dynamic compensation module corrects optical defocus in real time. According to the invention, full-detection coverage of nanoscale defects is realized, a defect transfer chain is actively blocked while the detection efficiency is improved, and the chip manufacturing yield and reliability are remarkably improved.

The invention provides an optical proximity effect correction method and system, a terminal and a medium, and the method comprises the steps: obtaining a plurality of initial parameter combinations of a photoetching mask design pattern, so as to form an initial population; wherein each initial individual in the initial population corresponds to a group of initial parameter combinations; determining a plurality of optimization indexes of the photoetching mask design graph, and determining an optical proximity effect correction function based on the plurality of optimization indexes and constraint conditions; and based on the optical proximity effect correction function, obtaining an optimal parameter combination of the photoetching mask design pattern in the iteration process of the initial population. According to the invention, the optimization algorithm is innovatively introduced into the field of optical proximity effect correction, comprehensive optical proximity effect correction is realized by introducing a plurality of optimization indexes, the manufacturing requirement of a high-precision silicon optical chip is effectively met, and the performance of the silicon optical chip is effectively improved.

The invention provides a wafer film thickness measuring method and device and chemical mechanical polishing equipment, the wafer film thickness measuring method comprises the following steps: a measuring spectrum and an interference spectrum are obtained, the measuring spectrum is formed by measuring light, and the interference spectrum is formed by reflected light after the measuring light is reflected by a wafer; calculating a correction coefficient according to the measured spectrum, and correcting the interference spectrum according to the correction coefficient; calculating a reflectivity curve of the wafer according to the corrected interference spectrum; and determining the film thickness of the wafer according to the reflectivity curve. According to the wafer film thickness measurement method, the influence of measurement noise on an interference spectrum is eliminated, the control precision of the wafer surface quality is improved, and the chip manufacturing yield is further improved.

The invention provides a crystal growth device and a crystal growth method, and solves the technical problems of low wafer utilization rate, low crystal growth speed, low efficiency, poor uniformity and the like in the existing chip manufacturing process. According to the invention, a traditional cylindrical ampoule structure is abandoned, and the annular ampoule design is innovatively adopted, so that the crystal grows into an inner hollow cylinder shape which is highly matched with the specification of a target wafer; the heater is arranged on the inner side of the ampoule, a traditional outer side heating mode is replaced, and heat is intensively acted on crystals in cooperation with an adjusting center of a heat preservation material during crystal growth, so that heat loss is reduced; the periphery of the heater is made of heat insulation materials, heat radiation leakage is effectively restrained, meanwhile, the ampoule supporting structure is adjusted, and the whole device is simple, low in cost and light in weight.

The invention provides an epitaxial wafer edge morphology compensation type wafer double-sided polishing device and method, and belongs to the technical field of semiconductor wafer ultra-precision machining. The polishing main machine comprises an upper fixed disc, a lower fixed disc and a wafer driving mechanism; the pressure loading system is used for applying adjustable pressure to the fixed disc; the polishing solution supply system is used for conveying a flow-adjustable polishing solution to the processing interface; the central control unit is in communication connection with the two systems and executes edge morphology compensation control logic, specifically, the machining pressure is adjusted in a segmented mode, and the flow of the polishing solution and the pressure are subjected to coupling change. According to the method, the atomic level flatness of the wafer surface is ensured, the edge morphology is accurately controlled, the edge thickening of the epitaxial layer is perfectly counteracted, and the photoetching yield of high-end chip manufacturing is remarkably improved.

The invention relates to the technical field of integrated circuit manufacturing, in particular to a wafer-level multi-chip metal wiring method and a wafer. Metal wires are arranged in a layered mode, and preset intervals are set for isolation; jumper connection between the metal wires of different metal layers is achieved through the through holes at the intersections of the scribing grooves, high-density signal transmission is achieved through the multiple layers of metal wires, and the situation that two adjacent metal wires are short-circuited together due to cutting extrusion during scribing can be prevented through cross-layer jumpers and interval isolation arrangement of the metal wires. By means of the layered metal wiring structure and spaced wiring, efficient data burning of thousands of chips on the wafer is achieved, stray capacitance and short circuit risks are remarkably reduced, meanwhile, the wafer utilization rate and burning efficiency are improved, the number and grouping mode of the chip arrays can be flexibly adjusted according to requirements, and the method is suitable for large-scale popularization and application. And the manufacturing requirements of chips with different scales are met.

The invention discloses a Micro-LED chip array integrated with a homogeneous micro-lens array and a preparation method thereof, and the method comprises the steps: carrying out the wafer-level precise bonding of a Micro-LED light-emitting pixel array and a CMOS drive circuit substrate, removing a substrate, integrating a homogeneous pixel-level GaN micro-lens array on a GaN-based pixel array through the photoetching, hot melting backflow and dry etching technologies, and carrying out the precise bonding of the micro-LED light-emitting pixel array and the CMOS drive circuit substrate. And finally, realizing the full-pixel common cathode conduction of the Micro-LED chip by adopting a metal interconnection process. According to the method, the Micro-LED pixel array and the micro-lens array are homogeneously integrated, are made of the same material and have no refractive index difference, so that no Fresnel loss exists on an interface, and the light extraction efficiency of a chip is improved. In addition, the method is simple in manufacturing process, low in cost, good in chip structure reliability, high in stability and suitable for being applied to industrial chip manufacturing.

The invention provides a chip testing method based on an ATE platform, and relates to the technical field of chip manufacturing and testing. According to the method, multiple advanced test technologies and intelligent algorithms are creatively integrated, test environment parameters are accurately controlled through an intelligent environment regulation and control system, radio frequency and digital signals are efficiently processed in cooperation with a test engine, a test execution stream optimizes a high-speed interface test by using a chip built-in Loopback function and an adaptive algorithm, and the test efficiency is improved. The intelligent control and analysis system dynamically adjusts a test process and accurately predicts chip defects based on a federal learning framework, and realizes Chiplet interconnection verification and closed-loop data analysis feedback optimization of a test program at the same time. The chip testing efficiency and precision are effectively improved, the testing cost is reduced, dependence on expensive equipment is reduced, the method can be widely applied to various chip testing scenes, and remarkable economic benefits and technical advantages are brought to chip manufacturing enterprises.

The utility model discloses a spot check machine for chip manufacturing, comprising a workbench, the top of the workbench is fixedly provided with an overturning assembly, the overturning assembly comprises a double-shaft cylinder and a moving frame, the double-shaft cylinder is fixedly installed on one side of the workbench, the moving frame is fixedly connected with the output end of the double-shaft cylinder, and the moving frame is fixedly connected with the output end of the double-shaft cylinder. An electric push rod is fixedly installed at the top of the movable frame, the output end of the electric push rod is fixedly connected with a toothed plate, one side of the movable frame is connected with a rotating shaft through a bearing, the side wall of the rotating shaft is fixedly connected with a first gear, and the first gear is connected with the toothed plate in a meshed mode. According to the sampling inspection machine for chip manufacturing, through the arranged overturning assembly, a chip can be overturned, so that the two faces of the chip can be detected, no omission exists in the detection process, the detection effect cannot be affected by omission, and the quality of a chip product is higher.

The invention belongs to the technical field of polyurethane, and provides polyurethane resin, polyurethane gloves and a preparation method and application thereof. The polyurethane resin is prepared from the following raw materials in percentage by mass: 5%-12.5% of modified organic silicon polyol, 5%-12.5% of bio-based polyol, 5%-8% of isocyanate, 0.01%-0.02% of an antioxidant, 0.001%-0.002% of a catalyst, 1%-2% of a chain extender, 0.1%-0.7% of polyether polyol, 0.02%-0.05% of a terminating agent and 71%-75% of a solvent, the preparation raw materials of the modified organic silicon polyol comprise a dihydroxyl-terminated organic silicon prepolymer and binary acid. The polyurethane glove prepared by compounding two specific polyhydric alcohol modified organic silicon polyhydric alcohol and bio-based polyhydric alcohol as well as other substances has good wear resistance and fingerprint-free characteristic, is easy to demould, and is suitable for the field of automobile film and chip manufacturing.

The invention relates to the technical field of semiconductor manufacturing, photoetching alignment and feature recognition, and particularly discloses a photoetching alignment compensation system and method based on feature targeting. An exposed pattern on the surface of a wafer is used as a unique target reference, a built-in visual imaging structure coaxial with a photoetching light path is adopted, a sub-pixel-level feature extraction and dynamic reference real-time updating mechanism is combined, the dynamic deformation of the wafer is calculated, high-frequency compensation of a workpiece table is achieved, and nanoscale overlay precision is achieved. The core improvement of the invention lies in that a light path coaxial visual integrated structure is designed to solve the problem of external imaging parallax; a feature point self-adaptive weighted matching algorithm is provided, and the deformation compensation precision is improved; and constructing a reference map real-time micro-updating mechanism, and eliminating progressive deformation drift of the wafer. The system does not need to manufacture a special physical alignment mark, continuously verify a feature matching state in the whole exposure process and quickly trigger safety protection when the matching degree is abnormal, is suitable for a photoetching alignment process for manufacturing advanced process chips of 3nm and below, has an alignment error of less than or equal to 1.1 nm under a 12-inch wafer standard test condition, reduces the dependence on an ultra-precise workpiece table, and has a good application prospect. The system has the advantages of autonomous controllability, high interference resistance and controllable cost.

The utility model discloses a lamp chamber heat dissipation structure and photoetching equipment, and relates to the technical field of photoetching equipment. The lamp chamber heat dissipation structure comprises a light source, a lamp chamber body, an air inlet assembly and an air exhaust assembly. The air inlet assembly and the air exhaust assembly are arranged at the two opposite ends of the lamp chamber body respectively. The lamp chamber body comprises a containing cavity defined by an upper lampshade and a lower lampshade which are oppositely arranged, and the light source is arranged in the containing cavity. The air inlet assembly comprises an air inlet hole communicating with the lamp chamber body, and the lamp chamber body communicates with the outside through the air inlet hole. The exhaust assembly comprises an exhaust channel communicating with the lamp chamber body, and the lamp chamber body communicates with the outside through the exhaust channel. Air enters the lamp chamber body through the air inlet hole and then is exhausted from an outlet of the exhaust channel through the upper lampshade and the lower lampshade in sequence. According to the lamp chamber heat dissipation structure, the heat dissipation effect in the lamp chamber can be improved, and then the temperature stability of a light source and the yield of chip manufacturing are guaranteed.

The invention relates to an overlay measurement system and a measurement method, and belongs to the technical field of chip manufacturing. Interference scanning focus measurement and independent focusing imaging of double industrial cameras are combined, an overlay measurement system accurately positions focal planes of different photoetching layers on a wafer by using interference signals through one-time vertical scanning, and then the two cameras are driven to be synchronized to image plane positions of the respective focal planes, so that the alignment precision of the wafer is improved. Therefore, one-time and synchronous high-definition imaging and overlay error calculation of two layers of patterns exceeding the optical focal depth are realized, and the measurement efficiency is remarkably improved.

The invention discloses a cross-batch chip identity verification method, device and equipment, a medium and a product, and relates to the technical field of semiconductor integrated circuit testing. The method comprises the following steps: collecting multi-source entropy data in a chip manufacturing environment, and fusing the multi-source entropy data to generate an original random sequence; intercepting the original random sequence based on the identification code length to obtain a basic identification code, and performing anti-prediction encryption processing to obtain an encrypted identification code; writing the encrypted identification code into a non-fuse nonvolatile storage area of the chip, verifying the storage integrity in real time, and activating a self-destruction circuit to cope with a failure scene; and constructing a distributed index associated with a wafer batch number, a chip physical coordinate and a test timestamp, performing double collision detection in a layered manner, and when it is detected that cross-batch identification codes are repeated, freezing identification code distribution of a defective machine and generating a traceability chain. According to the scheme, the security and uniqueness of chip identity verification are improved, and the traceability of problems in the chip production and test process is enhanced.

This invention discloses an integrated integrated circuit chip structure and its fabrication method. The invention relates to the field of thermal design and thermal control technology for integrated circuit chips, addressing the problem of weak heat transfer capabilities at high heat flux density points in existing integrated circuit chips. An integrated integrated circuit chip with electrical and heat dissipation functions is fabricated on a semiconductor substrate wafer and then packaged. By combining integrated circuit fabrication technology and microfluidic fabrication technology, microfluidic channels are directly fabricated on the semiconductor substrate wafer during integrated circuit chip fabrication, rather than being fabricated separately after chip fabrication. This enables the fabrication of heat dissipation structures for multiple integrated circuit chips, reducing the cost of chip heat dissipation. A cover plate guides the cooling medium into the microfluidic channels, allowing heat from high heat flux density points on the chip to directly exchange with the cooling medium after conduction through the substrate, reducing thermal resistance during heat loss and improving heat dissipation capacity.

The invention discloses a low-water-permeability and low-oxygen-permeability photoresist protective film and a preparation method thereof, and relates to the technical field of dry film photoresist protective films, the protective film comprises an inner layer, a middle layer and an outer layer, the inner layer is prepared from 100 parts of low-density polyethylene and 0.1-0.3 part of a release agent, and the middle layer is prepared from 0.1-0.3 part of a curing agent; the middle layer is prepared from 20-80 parts of low-density polyethylene, 10-40 parts of high-density polyethylene, 10-30 parts of a binder, 6-12 parts of modified silicon dioxide and 1-2 parts of an antistatic agent, and the outer layer is prepared from 10-90 parts of low-density polyethylene, 10-40 parts of metallocene low-density polyethylene and 0.1-0.5 part of an anti-sticking agent; according to the invention, excellent water and oxygen double barrier properties are realized, excellent protection can be provided for a dry film photoresist film, the dry film photoresist film has the characteristics of high mechanical strength, static resistance, clean stripping and the like, the process stability and the product yield in chip manufacturing are powerfully guaranteed, and the application value is remarkable.

The invention provides a performance prediction method for a hafnium oxide semiconductor material structure, and relates to the technical field of semiconductor material research and development. The method comprises the following steps: performing global search in an Hf-O binary system by using crystal structure prediction software, determining the most stable two-dimensional Hf2O4 crystal structure, and further confirming the crystal configuration through structure optimization; calculating an Hf2O4 crystal structure by using density functional theory calculation software, and evaluating the dynamic, thermodynamic and mechanical stability of Hf2O4 by using a calculation result system; the electronic property of the Hf2O4 is obtained through further deep calculation, and the structural stability and semiconductor characteristics of the Hf2O4 are verified. According to the invention, through the first principle and the evolutionary algorithm calculation, the simulation calculation is used to replace the traditional trial-and-error experiment, and the novel semiconductor material with high reliability can be efficiently explored; a theoretical basis is provided for the design of a novel high-performance semiconductor material in advanced chip manufacturing, the research and development period can be expected to be remarkably shortened, and the cost can be reduced.

The invention belongs to the technical field of semiconductor design automation, and provides a design rule checking method for a chip layout and related equipment. The method comprises the following steps: acquiring a to-be-processed chip layout comprising at least one graphic layer; a process rule interval of a target graph layer in the chip layout and factor weights of the target graph layer on a plurality of process risk factors are obtained, the process rule interval is the minimum graph interval meeting process production, and the factor weights are used for representing the interference degree of the corresponding process risk factors on chip manufacturing; calling a conflict quantification model to calculate a conflict risk value of each adjacent graph in the target graph layer based on the process rule spacing, the factor weight and the actual spacing of each adjacent graph in the target graph layer; and based on the conflict risk value, carrying out design rule check on the target graph layer. Through the technical scheme provided by the invention, the precision of chip layout design verification can be improved.

The utility model relates to the technical field of chip manufacturing waste recovery devices, and discloses a chip manufacturing waste recovery device which comprises a box body, the inner wall of the box body is connected with a storage box in a sliding mode, the top of the storage box is connected with a turning assembly and an air drying assembly, and the outer wall of the box body is connected with a shaking assembly. Compared with the prior art, the chip manufacturing waste recovery device has the advantages that in the chip manufacturing waste recovery device, the shaking assembly is used for conveniently driving waste in the storage box to shake up and down and make close contact with cleaning liquid, stains and impurities accumulated on the surface of the waste can be cleaned away, and the cleaning effect is improved; the overturning assembly is used for conveniently overturning the waste materials stacked together in the storage box, the contact area between the waste materials and the cleaning liquid is increased, and the cleaning efficiency is improved; and the air drying assembly is used for conveniently carrying out air drying treatment on water stains on the surfaces of the waste materials after the waste materials are cleaned, and subsequent recycling treatment is facilitated.

This reduces the likelihood that devices contained in a plate-like material will be damaged and / or that chips manufactured from the plate-like material will detach from the first and / or second sheets due to the application of external force to the plate-like material. [Solution] A fastening device for fastening a second sheet to a frame unit, which includes a frame having a through hole formed therein, a first sheet whose outer edge region is fixed to the frame so as to close one end of the through hole, and a plate-like object fixed to the central region of the first sheet so as to be positioned in the through hole, wherein the fastening device comprises a holding mechanism for holding the frame unit and a fastening mechanism for fastening the second sheet to the frame unit, the holding mechanism including a holding portion for applying an attractive force to the plate-like object through the central region of the first sheet and a raised portion for raising an intermediate region of the first sheet located between the outer edge region and the central region toward or beyond the other end of the through hole.

The utility model discloses a wafer soaking and developing device for manufacturing a biosensor chip, which comprises a developing device main body, a control table is fixedly arranged on the front surface of the developing device main body, a wafer soaking structure is fixedly connected to the bottom end of a partition plate, and a wafer fixing structure is arranged in the wafer soaking structure. The top end of the wafer fixing structure is provided with a control structure, the bottom end of the wafer soaking structure is fixedly connected with a solution circulating structure, the wafer soaking and developing device for manufacturing the biosensor chip is relatively simple in structure while the wafer developing quality and uniformity are ensured, the maintenance cost and difficulty are reduced, and the production efficiency is improved. Operators only need to set relevant parameters on the console, the operation is relatively easy, the wafer is developed in the closed soaking tank, the stability of the developing effect is greatly ensured, the adaptability of the device to wafers of different sizes is improved, the application range is expanded, the practicability and cost performance of the device are improved, and the device is more competitive in the market.

The invention discloses a device and method for taking down a wafer from a cutting adhesive tape, and relates to the technical field of chip manufacturing. Comprising a machine body and a vacuum cover installed on the top of the machine body. The controller is mounted outside the machine body; the fixing frame is mounted at the top of the machine body; the feeding mechanism is arranged above the machine body, the feeding mechanism is arranged in the fixing frame, the feeding mechanism comprises a cutting assembly and a feeding assembly, and the cutting assembly is used for pressing and cutting the cutting adhesive tape located on the feeding assembly; the device comprises a machine body, a vacuum cover and a taking-down mechanism, the taking-down mechanism is arranged above the machine body, the taking-down mechanism is arranged in the vacuum cover, the taking-down mechanism comprises a vacuum suction device, and the vacuum suction device is used for sucking and transferring raw materials located on the cutting adhesive tape. And the purpose of improving the use efficiency of the equipment is achieved.

This invention provides a method and apparatus for helical acoustic wave suspension constraint and motion control, belonging to the fields of biology, pharmaceuticals, chemical engineering, and semiconductor silicon chip manufacturing. The method utilizes multiple transducers to obtain focused helical acoustic waves, and uses these focused helical acoustic waves to achieve the suspension of matter in three-dimensional space, as well as control the spatial position and movement of the matter. This invention enables the suspension or movement of minute particles in space, achieving contactless operation and improving stability. Based on a special transducer position design, this invention achieves inward helical focusing of helical acoustic wave energy, with outward interference amplitudes canceling each other out, thereby maximizing the utilization of acoustic wave energy and achieving focused acoustic wave energy. This invention utilizes the combination of transducer array spatial position and acoustic wave phase to obtain a ring-shaped helical acoustic wave. This device can serve as a scientific research apparatus for further research into helical acoustic wave technology.

The invention discloses a processing method, device and equipment of a superconducting quantum chip, a medium and a program product, and belongs to the field of quantum chip manufacturing. The processing method of the superconducting quantum chip can be used for improving aging caused by drifting of room temperature resistance of superconducting quantum bits in the chip after the chip is manufactured. The processing method comprises the following steps: obtaining a position parameter and a processing parameter of a superconducting quantum bit to be processed; executing a positioning operation capable of positioning the electron beam to an irradiation position associated with the position parameter of the superconducting quantum chip to be processed; and enabling the electron beam to irradiate the superconducting quantum bits according to the processing parameters. According to the scheme, the aged superconducting quantum bits can be repaired, so that the performance requirements are met, and effective quantum calculation is carried out.

This invention relates to the field of chip packaging technology, specifically to a soldering vacuum furnace for chip manufacturing. It includes a vacuum furnace body, a base frame below the furnace body, and first cylinders on both sides of the base frame. Each first cylinder has a pneumatic telescopic rod, the telescopic ends of which are fixedly connected to the bottom of the vacuum furnace body. A double-layer support is fixedly mounted on the base frame, and the double-layer support can move up and down within the vacuum furnace body. A constant pressure core device is located within the double-layer support, and a swing coating brush is located on one side of the constant pressure core device. An intermittent rotating tray is rotatably connected to the bottom of the double-layer support, and an intermittent rotating bracket is located below the intermittent rotating tray. The intermittent rotating bracket contains an intermittent rotation mechanism fixedly connected to the bottom of the intermittent rotating tray. This invention provides a soldering vacuum furnace for chip manufacturing with better heat dissipation, allowing for the fixation of chips of different heights or thicknesses without damaging the chips or substrate.

A quantum-dot light conversion film, a preparation method and an application thereof and an anti-ultraviolet blue-free yellow light for chip manufacturing are provided. The preparation method includes: (1) mixing a quantum-dot concentrate with an acrylic monomer, then adding high polymer for secondary mixing, to obtain a polymer; (2) after mixing the polymer and nanoparticles, adding additives for dispersion to obtain a light conversion liquid resin; and (3) coating and curing the light conversion liquid resin to obtain a quantum-dot light conversion film. The light conversion film has high light conversion efficiency, adjustable emission peak position and narrow half peak width. Its surface forms a tightly arranged high refractive index microlens structure. When the light reaches the microlens array, as the light output surface is a lens structure and the refractive index is improved, more light is emitted in the positive direction, thereby effectively improving the light output rate.

The invention discloses an online in-situ characterization method of a chemical mechanical polishing through silicon via heterostructure, and belongs to the technical field of chip manufacturing. According to the TSV heterostructure sample, through the remarkable difference of different components of a TSV heterostructure sample matrix, an insulating layer, a barrier layer and a transmission layer in refractive index, work function and conductivity, a PiFM is taken as a core, a KPFM and a CAFM are combined, and the TSV heterostructure sample can be detected on the same platform by detecting light induction force, surface potential and current signals at a needle tip-sample position. And the real-time in-situ measurement of the TSV sample surface appearance height, roughness and interface component change is realized. According to the method, the light, electricity and force response differences between TSV heterostructure materials are fully utilized, dynamic feedback of the structure morphology and components in the CMP process is achieved, and support is provided for nano-scale and even atomic-scale polishing precision control.

The present application relates to the chip manufacturing technical field, specifically for the photonic chip multilayer overlay precision monitoring and calibration system based on image recognition, including: image acquisition module gathers super-resolution microscopic image, photoetching machine motion parameter, photoetching cavity environmental variable and overlay alignment data;Overlay alignment digital twin module constructs photoetching machine and wafer digital twin, combines chip layout and process parameters, simulates multilayer overlay deviation, exposure distortion and interlayer coupling effect through strict coupling wave analysis and rigid body kinematics algorithm;Overlay deviation intelligent analysis hub adopts YOLO-Transformer model, identifies deviation mode and locates deviation source;Visual calibration strategy generation unit constructs three-dimensional photoetching virtual scene, renders alignment and exposure process and generates calibration strategy;Self-adaptive alignment calibration unit predicts deviation trend according to calibration data, dynamically adjusts photoetching machine parameter. Thus, the problems of calibration inefficiency, insufficient precision and the like in the prior art are solved.

The invention discloses a quantum bit, a quantum chip and a quantum computer, and belongs to the technical field of quantum chip manufacturing. The quantum bit is arranged on the substrate and comprises a Josephson junction arranged on the surface of the substrate; the two through holes are adjacent to the Josephson junction, penetrate through the substrate and are used for forming a bit capacitor, and the bit capacitor and the Josephson junction jointly form the quantum bit. Through the above mode, the through hole type bit capacitor provided by the invention occupies a smaller area on the surface of the substrate, so that more quantum bits can be arranged on the limited surface of the substrate.

The application discloses an online enrichment detection system for particles and dissolved pollutants in water, which comprises a fly ash enrichment cavity, an interior of which is used for containing water, and a fly ash enrichment area between a liquid surface of the water and a top surface of the fly ash enrichment cavity; a bubble generating device arranged in the water in the fly ash enrichment cavity and used for generating bubbles for enriching particles and dissolved pollutants in the water; a gas sweeping device used for sweeping pure gas into the fly ash enrichment area and carrying away fly ash generated by the breaking of the bubbles; and a fly ash aerosol detection device used for detecting the concentration or particle size distribution of the particles in the fly ash and qualitatively and quantitatively analyzing the dissolved pollutants. The system can reliably detect low-concentration particles with a particle size of 6 nm or below in the water online, and qualitatively and quantitatively analyze the dissolved pollutants, so as to provide more accurate real-time water data for advanced chip manufacturing processes, environmental water detection, drinking water detection and industrial wastewater detection. The application further discloses an online detection method for particles and dissolved pollutants in water.