438 results about "Chip fabrication" patented technology

A dicing sheet with a protective film forming layer has a substrate film, an adhesive layer, and a protective film forming layer, and at a minimum, the adhesive layer is formed in an area surrounding the protective film forming layer in a planar view, and the substrate film has the following characteristics (a)-(c): (a) the melting point either exceeds 130° C. or the film has no melting point; (b) the thermal contraction rate under conditions of heating at 130° C. for two hours is from −5 to +5%, and (c) the degree of elongation-to-break in the MD direction and the CD direction is at least 100%, and the stress at 25% is no more than 100 MPa.

This invention provides novel high density memory devices that are electrically addressable permitting effective reading and writing, that provide a high memory density (e.g., 10¹⁵ bits/cm³), that provide a high degree of fault tolerance, and that are amenable to efficient chemical synthesis and chip fabrication. The devices are intrinsically latchable, defect tolerant, and support destructive or non-destructive read cycles. In a preferred embodiment, the device comprises a fixed electrode electrically coupled to a storage medium having a multiplicity of different and distinguishable oxidation states wherein data is stored in said oxidation states by the addition or withdrawal of one or more electrons from said storage medium via the electrically coupled electrode.

A method for identifying lithographically significant defects. A photomask is illuminated to produce images that experience different parameters of the reticle as imaged by an inspection tool. Example parameters include a transmission intensity image and a reflection intensity image. The images are processed together to recover a band limited mask pattern associated with the photomask. A model of an exposure lithography system for chip fabrication is adapted to accommodate the band limited mask pattern as an input which is input into the model to obtain an aerial image of the mask pattern that is processed with a photoresist model yielding a resist-modeled image. The resist-modeled image is used to determine if the photomask has lithographically significant defects.

Systems and methods for process simulation are described. The methods may use a reference model identifying sensitivity of a reference scanner to a set of tunable parameters. Chip fabrication from a chip design may be simulated using the reference model, wherein the chip design is expressed as one or more masks. An iterative retuning and simulation process may be used to optimize critical dimension in the simulated chip and to obtain convergence of the simulated chip with an expected chip. Additionally, a designer may be provided with a set of results from which an updated chip design is created.

The present invention reveals a semiconductor chip structure and its application circuit network, wherein the switching voltage regulator or converter is integrated with a semiconductor chip by chip fabrication methods, so that the semiconductor chip has the ability to regulate voltage within a specific voltage range. Therefore, when many electrical devices of different working voltages are placed on a Printed Circuit Board (PCB), only a certain number of semiconductor chips need to be constructed. Originally, in order to account for the different demands in voltage, power supply units of different output voltages, or a variety of voltage regulators need to be added. However, using the built-in voltage regulator or converter, the voltage range can be immediately adjusted to that which is needed. This improvement allows for easier control of electrical devices of different working voltages and decreases response time of electrical devices.

A chip transfer method for LED (light-emitting diode) wafer level package includes the steps: manufacturing an LED unit device array on an LED epitaxial wafer, manufacturing metal layers on parts of unit devices of the unit device array to serve as middle metal layers in bonding, and forming a unit device array to be bonded; manufacturing metal patterns corresponding to electrodes of the unit device array to be bonded on the front surface of a base plate, forming heat conduction channels and electric conduction channels below the metal patterns, and connecting electrodes of an LED unit device with a metal bonding pad on the back surface of the base plate through the electric conduction channels; conversely mounting the unit device array to be bonded on the base plate in a bonding mode; finally, sequentially stripping the unit devices to be bonded in a laser stripping mode, separating the epitaxial layers of the unit devices to be bonded from a substrate, and forming a whole film LED array by the separated epitaxial layers and the base plate. The chip transfer method can be used for wafer level package of the LED devices, package efficiency is improved, and cost is reduced.

This invention provides novel high density memory devices (FIG. 3) that are electrically addressable permitting effective reading and writing, that provide a high memory density (102), that provide a high degree of fault tolerance, and that are amenable to efficient chemical synthesis and chip fabrication. The devices arc intrinsically latchable, defect tolerant, and support destructive or non-destructive read cycles. In a preferred embodiment, the device comprises a fixed electrode electrically coupled to a storage medium having a multiplicity of different and distinguishable oxidation states wherein data is stored in said oxidation states by the addition or withdrawal of one or more electrons from said storage medium via the electrically coupled electrode.

A flip chip having solder bumps and an integrated flux and underfill, as well as methods for making such a device, is described. The resulting device is well suited for a simple one-step application to a printed circuit board, thereby simplifying flip chip manufacturing processes which heretofore have required separate fluxing and underfilling steps.

Defects are detected in a reticle used in integrated circuit chip fabrication by obtaining digital image data corresponding to an image of the reticle. Typically, this is accomplished by scanning the reticle using a laser scanner. The digital image data are then processed according to predetermined criteria to identify defects. Such processing may include, for example, processing the digital image data in comparison to reference digital image data for the same or a similar portion of the reticle. Next, a response that would be produced if the reticle were to be utilized in a photolithographic system is simulated by processing the digital image data corresponding to the reticle.

A bipolar CMOS DMOS (BCD) integrated device based on a N type extension layer and a manufacture method thereof, which belongs to the semiconductor power device technology field, are disclosed. In the invention, a high voltage nLDMOS device, a high voltage nLIGB device, a low voltage PMOS device, a low voltage NMOS device, a low voltage PNP device and a low voltage NPN device are integrated on a same substrate. All devices are made in an N type extension layer arranged on a surface of a P type extension layer which is on a surface of a P type substrate. And junction isolations of the devices are realized through P<+> isolation regions. N type buried layers are arranged between the P type substrate and the P type extension layer, wherein the P type substrate and the P type extension layer are under the high voltage devices. N type buried layers are/ are not arranged between the P type extension layer and the N type extension layer, wherein the P type extension layer and the N type extension layer are under the low voltage devices. The N type buried layers are introduced in the invention to realize that silicon chips with lower resistivity can be used as the substrate at a same breakdown voltage. In the prior art, float-zone technique is adopted to manufacture monocrystalline silicon pieces, which can increase the chip manufacturing costs. In the invention, the float-zone technique is not used so that the chip manufacturing costs can be reduced.

The invention provides a method of making silicon-on-insulator SOI substrates with nitride buried insulator layer by implantation of molecular deuterated ammonia ions ND₃⁺, instead of implanting nitrogen ions (N⁺, or N₂⁺) as is done in prior art nitride SOI processes. The resultant structure, after annealing, has a buried insulator with a defect density which is substantially lower than in prior art nitride SOI. The deuterated nitride SOI substrates allow much better heat dissipation than SOI with a silicon dioxide buried insulator. These substrates can be used for manufacturing of high speed and high power dissipation monolithic integrated circuits.

The invention discloses a switching power source and a starting circuit of the switching power source, wherein, the starting circuit is used for the power supply of a PWM control chip that is used for controlling the switching of the power FET; under the starting mode, the power for the PWM controlling chip is supplied by a starting circuit capacitor with smaller capacity value, thereby guaranteeing that the system has short starting time; after the starting is successful, under the normal working mode, a larger capacitor is connected with the starting circuit capacitor in parallelism through a switch to supply power for the PWM controlling chip, thereby reducing the ripples of the power-supply voltage of the switching power source in normal work and improving the stability of the system. Using the switching power source of the starting circuit prevents a high-voltage element from being introduced into the PWM controlling chip, thereby reducing the production process requirement of the chip, reducing the production cost of the PWM chip and reducing the starting time of the system as far as possible while reducing the power consumption.

The invention discloses a high-brightness LED chip fabrication method, which comprises the following steps: generating an epitaxial wafer on a sapphire substrate; depositing a SiO2 film on the epitaxial wafer; etching an N-region patter on the chip by photolithography using the SiO2 film as the mask; cleaning the SiO2 not protected by the photoresist using a corrosive solution; cleaning with a photoresist removing solution to remove the photoresist; etching N steps and a track with the size of the chip to expose the n-GaN mesa; roughening the N-GAN surface by light-assisting wet etching; depositing an ITO film on the epitaxial wafer surface by evaporating; and evaporating a Cr/Ni/Au P-N electrode. The method can improve the external quantum efficiency of the LED device by increasing the probability of light refraction from the n-GaN to the air. The method can be used for fabricating normal LED chip and vertical LED chip, and has the advantages of simple process and low cost. The method suits industrial production and can greatly improve the external quantum efficiency.

A silicon Raman laser that can be electrically switched or modulated and which demonstrates active mode-locking capabilities. The laser can be used with a more traditional glass fiber cavity, or can be fabricated on a single chip with a cavity, or a cascaded cavity, in which the chip fabrication is compatible with widely used silicon chip fabrication methods. The laser can be tuned by adjusting a source pump laser to produce specific output and operates at room temperature. Output is present in the near- and mid-infrared frequency range, and the laser can simultaneously produce output at the Stokes and at the anti-Stokes wavelengths.

The invention discloses an inverted high-voltage light emitting diode (LED) chip electrode and a chip fabrication method. The chip electrode comprises a substrate and an epitaxial layer, wherein the epitaxial layer comprises a P-type GaN layer, a quantum well region and an N-type GaN layer, unit chips which are independent to each other are arranged on the epitaxial layer, each unit chip forms a patterned P-type GaN platform and a patterned N-type GaN platform, more than two groups of unit chips form a high-voltage chip unit, the P-type GaN platform and the N-type GaN platform both adopt a metal electrode to interconnect, the metal electrode comprises a P-type metal reflection electrode, a P-N interconnected electrode, an N-type metal electrode and a bonding pad electrode, and the side wall from the P-type GaN platform and the N-type GaN platform and a deep groove region where the unit chips are interconnected adopt a DBR structure to connect. With the inverted high-voltage LED chip electrode disclosed by the invention, the light emergent efficiency of the chip is improved, the contact area of a bonding pad for chip package is expanded, the stability is improved, the current clustering effect is reduced, moreover, wireless welding is achieved, the cooling effect is good, cost is favorably reduced, and light attenuation is reduced.

Circuits and methods for protecting against intellectual property piracy and integrated circuit piracy from an untrusted third party are provided. A circuit can include an original circuit and an obfuscated circuit incorporated into the original circuit and changing the output of the original circuit, wherein the obfuscated circuit is configured to recover the output of the original circuit by modifying the obfuscated circuit. In addition, a method of manufacturing a semiconductor device can include designing a circuit including an original circuit and an obfuscated circuit, and fabricating the circuit, wherein the obfuscated circuit is configured to change an output of the original circuit and to recover the output of the original circuit by modifying the obfuscated circuit.

The invention discloses a simple manufacturing method of a high-efficient light emitting diode chip. The method comprises the following steps that an epitaxial luminescence structure is formed on a substrate; a non-conducting material is evaporated on an ohmic contact layer so as to be taken as a current barrier layer; silicon dioxide is evaporated on an epitaxial luminescence structure surface and a side surface; all the photoresists on the surface are removed and evaporation is performed on the surface to form an ITO conducting layer; an etchant solution is used to remove the silicon dioxide on the epitaxial luminescence structure side surface and an N-type electrode manufacturing area; silicon nitride is evaporated on a chip surface, a side surface and an electrode isolation groove between an N-type electrode and an epitaxial layer to form a chip protection layer and an electrode isolation layer; a P-type electrode manufacturing area and the N-type electrode manufacturing area are defined on the chip surface; the photoresist is evaporated on and peeled off the P-type electrode manufacturing area and the N-type electrode manufacturing area; the chip is splintered and is separated into independent chip grains. By using method in the invention, a chip manufacturing technology is effectively simplified; chip process time is shortened; chip manufacturing cost is reduced and chip quality is increased.

[Problem] To provide a dicing sheet with a protective film forming layer, provided with a precut and hardened protective film forming layer, wherein when the dicing sheet is fabricated, the protective film forming layer is not deformed even when subjected to die punch processing using a die cutter. [Solution] This dicing sheet with a protective film forming layer (10) is characterized in that a hardened protective film forming layer (4) is temporarily affixed, so as to be peelable, to the inner circumference of a support body (3) having an adhesive section on the outer circumference thereof, and the storage elasticity coefficient of the protective film forming layer at 23°C prior to hardening is 0.6-2.5 GPa.

The invention provides a universal chip test system, a universal chip test method and a storage medium. The chip test system comprises a main control device, a test mainboard, N daughter board connecting pieces, a plurality of test daughter boards and a plurality of test suites. The test mainboard is connected with the main control device, the test suites and the test daughter boards; the test daughter boards match the test suites, and the test daughter boards are connected with the test mainboard through daughter board connecting pieces. The universal chip test system provided by the invention can quickly and accurately verify and test functions and performances before and after chip design, can meet test tasks of function verification, performance test and reliability test before chip manufacturing, adopts a modular design, is high in expandability, and test automation can be realized.