64 results about "Design Validation" patented technology

A method and apparatus for producing a verification of digital circuits are provided. In an exemplary embodiment on the invention, a plurality of verification scopes of an integrated circuit design as defined as part of a verification plan. A plurality of verification runs are executed within two or more verification scopes defined by the verification plan. At least two verification runs are selected to merge verification results together. Like named scenarios are merged together for each verification scope to generate merged verification results that are then stored into a merge database. A verification report is generated for the integrated circuit design from the merged verification results. A merge point may be specified so like named subtrees and subgroups may be merged across different verification scopes of selected verification runs. The merge point may combine check and coverage results obtained during simulation with check and coverage results obtained during formal verification.

A method for derivation and abstraction of test models for validation of industrial designs using guided simulation is described. The method employs automatic abstractions for the test model which reduce its complexity while preserving the class of errors that can be detected by a transition tour. A method for design validation comprising generating a state-based test model of the design. The test model is abstracted by retiming and latch removal. Finally, a validation technique is applied on the abstracted test model. First, the number of internal (non-peripheral) latches in a design is minimized via retiming using a method of Maximal Peripheral Retiming (MPR). According to the MPR method, internal latches are retimed to the periphery of the circuit. Subsequently, all latches that can be retimed to the periphery are automatically abstracted in the test model. The validation technique may comprise of model checking, invariant checking or simulation using test sequences generated from the abstracted test model.

Functional coverage techniques during design verification using cross-product coverage models and hole analysis are enhanced by the use of coverage queries. After running a test suite, a core set of non-covered events is specified. A coverage query is then automatically constructed and executed on the test results to identify a hole in the functional coverage that satisfies conditions of the coverage query and includes the core set. The results of the query are presented as a simplified view of the coverage of the events in the cross-product space. Use of coverage queries allows a verification team to focus on specific areas of interest in the coverage space and to deal practically with highly complex coverage models. It also avoids the burden of producing and evaluating complete hole analysis reports.

A preemptive reloading technique is employed in a test program generator. Initialized resources are reset with needed values by reloading instructions. The actual reloaded value is chosen later, when the instruction that actually needs the value is generated. The test program generator distances the reloading instruction from the instruction that actually needs the value, thus making it possible to avoid fixed test patterns and to generate interference-free test segments during design verification.

A method for design validation of complex IC with use of a combination of electronic design automation (EDA) tools and a design test station at high speed and low cost. The EDA tools and device simulator are linked to the event based test system to execute the original design simulation vectors and testbench and make modifications in the testbench and event based test vectors until satisfactory results are obtained. The event based test vectors are test vectors in an event format in which an event is any change in a signal which is described by its timing and the event based test system is a test system for testing an IC by utilizing the event based test vectors. Because EDA tools are linked with the event based test system, these modifications are captured to generate a final testbench that provides satisfactory results.

A method of designing a validation environment for a service implemented by an embedded electrical system. In the method one or more user requests and system responses are assigned. Next, a behavioral automata is assigned to the service, which fixes the allowed sequencing of the user requests and system responses. Then, a skeleton validation environment is automatically generated for the service. The skeleton validation environment includes testing automata produced from a traversal of the behavioral automata, a model of initial conditions, models of user requests, models of system response accuracy, an environmental model, and the dataflow and control flow assembling these models together. The skeleton validation environment covers all user requests and resultant system responses of the service. The skeleton validation environment is then recorded in a computer readable memory device for use by a design validation tool.

The invention discloses an FPGA (filed programmable gate array) fault automatic diagnosing method based on a knowledge database. The method includes: structuralizing fault information during storage FPGA design and verification; performing fault search according to feature information a new fault case, matching most related and similar fault information according to information such as fault generation and fault feature, and displaying detailed contents and fault solutions to solve the new fault. Acquired fault experience and methods during FPGA design verification are used to build a knowledge database system, detailed fault information and solutions are displayed visually, faults can be positioned accurately, conveniently and fast, and fault debugging and solving efficiency of FPGA design verification staff is increased greatly.

A fast and economical system and methods directed to low-fidelity fabrication of three-dimensional (3D) objects using 3D printing. The invention facilitates rapid prototyping by providing a wireframe structure in the form of the underlying design structure of a 3D model, which may be useful for a variety of reasons including to provide a prototype preview that may be used for design validation of a 3D model.

Techniques and mechanisms for the use of layout-versus-schematic (LVS) design tools to validate photonic integrated circuit designs. Various implementations employ alternate analysis techniques with LVS analysis tools to perform one or more LVS analysis processes on photonic integrated circuits. These analysis processes may include curvilinear design validation and the associated flow implementations.

The invention discloses an on-chip power supply network verification method for a side channel attack. The method comprises: logical synthesis and physical design processing is carried out on a register transmission level netlist file of a chip to obtain a transistor level netlist file; according to the obtained transistor level netlist file, a circuit model including a power supply network and a load is established; according to a generated plaintext-ciphertext data pair and a corresponding secret key, a logic process for encryption operation execution on the chip is simulated to obtain a current waveform file of the load; on the basis of the circuit model and the current waveform file of the load, a physical process for encryption operation execution on the chip is simulated to obtain a power consumption curve of the chip; according to the obtained power consumption curve, a side channel attack is carried out on the chip to obtain a guess secret key of the attack; and on the basis of the obtained guess secret key, a side channel attack result is analyzed and an anti-side channel attack capability of the power supply network is verified. The method has advantages of low cost, high accuracy, and reduced design verification period.

The invention discloses an airborne system digital design verification system and method and belongs to the technical field of system engineering. The system disclosed by the invention comprises a top-layer digital design system and a domain engineering layered digital design system, wherein the top-layer digital design system comprises a demand analysis module, a top-layer analysis design module and a top-layer model test and verification module; and the domain engineering layered design system comprises a single-domain analysis design module, a single-domain test and verification module, multi-domain collaborative design module and a multi-domain model simulation verification module. The method disclosed by the invention comprises the following two steps: concept model machine design of an airborne system and virtual model machine design of the airborne system, wherein the former step comprises the following three sub-steps: demand analysis of the airborne system, system analysis of the airborne system and system design of the airborne system. The system and method disclosed by the invention can be used for supporting the digital analysis, design and verification of the airborne system, realizing 'design and verification first, implementation later' of the airborne system, avoiding the problems of long period, high cost, great risk and the like caused by the 'design and implementation first, verification later' of the traditional design method.

The invention provides a method for detecting and isolating software bugs and generating a minimal set of stimuli to reproduce the bugs. The present invention utilizes a recursive algorithm to compare the output of successively smaller software blocks of a program in development to a verified output sample. The smallest software blocks which are found to contain a bug are isolated. For each of these isolated blocks, the smallest input vector is determined such that the application of this vector to the block expresses the bug. The present invention utilizes a separate recursive algorithm to determine these minimal vectors.

A system and method for designing a dial plan for Voice over Internet Protocol (VoIP) systems includes generating an abstract dial plan design which is platform independent, the dial plan including rules for routing communications in a VoIP network structure. The dial plan is validated through simulations prior to deployment to evaluate the dial plan performance under simulated conditions. The dial plan design is translated to provide compatibility with a deployed network using platform specific configuration adaptors.

Validation of full-chip power distribution networks can be performed very early, and continuously throughout the design cycle, to detect real physical power connection problems and enable early correction of power grid designs using early floor plan and power grid design data. Common power connection and distribution errors are automatically addressed as an integral part of the early chip floor planning and chip power build processes providing efficient solutions requiring no extra wiring resource to be implemented and reducing the runtime of required final full-chip physical design checks, and the overall design cycle.

The invention discloses a prototype-based human-computer interaction design implementation method and system, and relates to the field of software development. The method comprises the steps of drawing all visual elements in a core function interface, combining all the visual elements through a preset combination rule, and generating a prototype according to a combination result and a selected prototype model; analyzing an interface of the prototype, and identifying a page set contained in the prototype; and converting the pages in the page set into a Qss style sheet file and a UI resource file according to a preset control mapping rule. Demand verification and design verification can be conveniently carried out at any time; the cost of a development system is estimated more accurately, research and development control points are moved forwards, development risks are reduced, a model library is automatically generated by using a software conversion tool according to a prototype system,the model library in the corresponding field is continuously created, accumulated and perfected, and subsequent inheritance and use of new research models can be facilitated.

Disclosed is a method for automatically testing the deskew setting for the clock in a parallel data interface. The deskew value is varied to a high and a low limit to the point where errors occur when transmissions occur. After determining the high and low operable limits of the deskew values, an optimum deskew setting may be determined and set for the system. The present invention may be used as a design verification technique, for optimizing a system after integration, or for further optimization of the deskew value after performing a training pattern for optimizing transmission performance.

The embodiment of the invention discloses a transformer and a power supply device. The transformer comprises a primary winding, a secondary winding, a shielding winding and an adjustable impedor; thefirst end or the second end of the primary winding is connected with the first end of the adjustable impedor, and the second end of the adjustable impedor is connected with the first end of the shielding winding; the adjustable impedor is a replaceable or adjustable impedance component; under the situation that the transformer is in access into a power supply circuit, when a switching tube of thepower supply circuit is switched between disconnecting and closing states, the direction of current produced by the shielding winding is opposite to the direction of the common mode current of the primary winding and the secondary winding, the adjustable impedor is used for adjusting the size of the current produced by the shielding winding, and the current produced by the shielding winding is equal to the sum of the common mode current produced by the primary winding and the secondary winding; wherein the number of turns of the shielding winding is a fixed value and larger than the thresholdvalue of the number of turns. According to the transformer and the power supply device, design and commissioning of the transformer can be simplified, the design validation cycle of the transformer isshortened, and the production cost is reduced.

An operational amplifier and a method for amplifying a signal. Embodiments provide a convenient and effective mechanism for reducing die area, design time and design verification time by sharing compensation components between the common-mode and differential feedback networks of the operational amplifier. As such, fewer compensation components are required, thereby reducing component die area. Additionally, given that the compensation components are shared between the common-mode and differential feedback networks, the feedback networks can be stabilized together with fewer compensation components to specify and verify, thereby reducing design and design verification time. Further, embodiments provide a compensation component coupling which does not couple directly to virtual ground, thereby reducing the noise of the operational amplifier.

A system and method for design verification and, more particularly, a hardware simulation accelerator design and method that exploits a parallel structure of user models to support a large user model size. The method includes a computer including N number of logic evaluation units (LEUs) that share a common pool of instruction memory (IM). The computer infrastructure is operable to: partition a number of parallel operations in a netlist; and send a same instruction stream of the partitioned number of parallel operations to N number of LEUs from a single IM. The system is a hardware simulation accelerator having a computer infrastructure operable to provide a stream of instructions to multiple LEUs from a single IM. The multiple LEUs are clustered together with multiple IMs such that each LEU is configured to use instructions from any of the multiple IMs thereby allowing a same instruction stream to drive the multiple LEUs.