43 results about "Design Validation" patented technology

The invention provides a DFT test task management method and device, electronic equipment and a storage medium, and belongs to the technical field of chip design verifier.The DFT test task management method comprises the steps that a data model is constructed on the basis of a design module list and a test step list, the data model is used for indicating testability design DFT test steps of all design modules, and the test steps of all the design modules are stored in the test step list; the data model comprises a plurality of DFT test tasks, attributes of each DFT test task comprise a selection state, and the selection state comprises a selected state and a non-selected state; based on the interactive input, determining at least one DFT test task of which the selection state is selected as an executable DFT regression object; and according to the DFT regression object, driving a DFT test task to be executed. According to the method, the DFT test tasks are normalized through the data model, only the DFT test tasks need to be selected for making the test plan, efficient management of the DFT test tasks is achieved, and the regression test efficiency is improved.

Digital model platform that enables the streamlined creation and management of digital twins and physical twins by leveraging external feedback and artificial intelligence (AI) is disclosed. Methods and systems for a model collaboration platform that facilitate the integration of external feedback, whether from physical, virtual, or human sources, into the streamlined design, validation, verification, certification, assembly, operations, and maintenance processes of complex systems. Updated results are output to those external sources, including physical twins, other digital twins or models and simulations, and / or human users. External feedback includes feedback data from physical prototypes and their environment, virtual prototypes, simulations, and subject-matter experts. Embodiments are directed to integrating external feedback into the assembly and system-level assessment of digital twins, physical twins, digital threads, and the iterative design of constituting digital engineering models, including constructing, maintaining, and improving digital engineering models for the design, validation, verification, certification, operations, and maintenance of complex systems.

The invention relates to an engineering construction stage user multi-dimensional demand analysis system and method, and the system comprises a multi-modal semantic model construction module which integrates a multi-source knowledge base, and extracts triple description statements from the provisions of the multi-source knowledge base to construct an engineering object ontology knowledge graph; the demand structured guidance and intelligent analysis engine module dynamically identifies an engineering stage and a user role, guides a user to perform text demand input, and performs semantic completion and standardization processing; the demand conflict detection and coordination correction module is used for detecting conflicts in user demands and generating a conflict influence analysis report and a coordination processing scheme; the intelligent drawing and dynamic optimization module is used for automatically drawing according to the triple obtained through demand analysis; and the demand analysis visualization and flow closed-loop module is used for generating an executable parameterized demand document and an association chart, and completing demand-design-verification engineering closed-loop management, so that intelligent analysis and standardization of user multi-dimensional demands are realized, and the system has the advantages of high efficiency, accuracy and intelligence.

The invention provides a chip design verification method and system, electronic equipment and a storage medium. The chip design verification method comprises the following steps: acquiring a design file of a chip and a design stage corresponding to the design file; selecting a target collaborative verification mode matched with the design stage from a plurality of collaborative verification modes; wherein the cooperative verification mode comprises a mode for verifying the design file through cooperation between logic simulation verification and form verification; the collaborative verification modes corresponding to different design stages are different, and the collaborative modes between logic simulation verification and form verification in the different collaborative verification modes are different; and verifying the design file based on the target collaborative verification mode. According to the method, logic simulation verification and formal verification work cooperatively, and respective advantages are combined for complementation, so that the efficiency and effectiveness of chip design and verification are improved.

The invention provides a multi-modal knowledge graph generation method and system for hardware design analysis, which break through design, verification and physics, realize information barriers among the three traditional EDA (Electronic Design Automation) fields, perform semantic fusion and association on information from different data fields, create a unified and queriable hardware design knowledge representation, and improve the reliability of hardware design analysis. And a coherent and operable unified knowledge model is formed. A multi-modal design knowledge graph is created by integrating a simulation result (dynamic data) and a physical implementation feature (performance data) into a static structure model, and a comprehensive design model with structure, behavior and performance features is analyzed in a unified framework. An engineer does not need to manually switch between different tools and data formats, but can access all-dimensional information about a static structure, a dynamic behavior and a physical property of a design through a single query interface.

The invention relates to the technical field of chip design verification, in particular to a monitor-based request analysis system, which is characterized in that a monitor is deployed on a key path to obtain transmission information in a case simulation process, and the transmission information is stored in a target file; according to the method, the request and the return of the cache unit can be formatted and stored in an information transmission manner, so that the specific request can be searched and extracted directly according to the target file subsequently, error analysis can be carried out only for the specific request, and the request analysis efficiency of the cache unit is effectively improved.

This application provides an instruction verification method, apparatus, device, and storage medium, relating to the field of chip design verification technology. The method includes: dividing the instruction to be verified according to a preset multi-layer instruction structure to obtain at least one instruction block corresponding to the multi-layer instruction structure; the instruction to be verified is a composite instruction including multiple basic instructions; the multi-layer instruction structure is used to characterize the basis for dividing the instruction blocks from the perspective of instruction function, and each instruction block has its own function; randomly generating a first verification instruction block based on a first instruction block, and generating a second verification instruction block based on the first verification instruction block and a second instruction block; wherein the first instruction block is an instruction block without constraints on other instruction blocks, and the second instruction block is constrained by the first instruction block; obtaining verification instructions based on each verification instruction block corresponding to at least one instruction block; and verifying the instruction to be verified using the verification instructions. This improves the random efficiency and fairness of instruction verification.

The invention discloses an instant simulation method of a design end, which belongs to the technical field of design simulation of a certain type of aircrafts, and comprises the following steps: S1, selecting a simulation object, S2, analyzing data correlation, S3, marking and summarizing the simulation object, S4, generating a simulation data template and filling and importing the simulation data template by a user, S5, setting a step length and starting simulation, and S6, gradually simulating. The real-time simulation capability is integrated at the design end, design and simulation integration is achieved, the problem of low efficiency caused by separation of design and simulation in a traditional process is effectively solved, the fixed-version data is obtained and verified in real time, the consistency of full-link data is ensured, simulation result distortion is avoided, and meanwhile, the design efficiency is improved. A direct assignment mode provided by the system enables designers to rapidly and flexibly assign variables in a complex logic expression, design verification and an iteration period are greatly accelerated, in addition, a complete simulation process record and a template reuse function support a rapid regression test, and the simulation working efficiency and the knowledge reuse value are remarkably improved.

The embodiment of the invention relates to the technical field of reactor testing, in particular to a method for determining the reduction proportion of a simulated reactor core of a simulated reactor relative to an actual reactor core of an actual reactor, the simulated reactor, a design verification and safety checking method of the reactor and a computer storage medium. According to the method for determining the reduction proportion of the simulated reactor core of the simulated reactor relative to the actual reactor core of the actual reactor, the resistance characteristic, the rod bundle heat exchange characteristic and the flow distribution characteristic of the simulated reactor core of the simulated reactor are considered to be similar to those of the actual reactor core of the actual reactor, so that the simulated reactor can meet similar requirements of a natural circulation experiment; the flow heat exchange characteristic of the actual reactor core in natural circulation can be accurately reproduced in a natural circulation experiment; moreover, by determining the proportion of the number of the fuel assemblies of the actual reactor reduced to the number of the fuel assemblies of the simulated reactor, the number of the fuel assembly simulators of the simulated reactor can be greatly reduced under the condition of ensuring the simulation precision, and the experiment cost of the natural circulation experiment is reduced.

The application relates to the technical field of chip design verification, in particular to a request analysis system based on a monitor, which deploys the monitor on a key channel to acquire transmission information in a use case simulation process and stores the transmission information into a target file, so that the request and return of a cache unit can be stored in a transmission information format, the subsequent search and extraction of specific requests can be directly performed according to the target file, and then error analysis can be performed only on specific requests, so that the request analysis efficiency of the cache unit is effectively improved.

The application discloses a chip design verification system and method, an electronic device and a storage medium, and relates to the technical field of integrated circuit design. Since the excitation descriptor chain table generated by the dynamic scheduler according to the target test scene can directly present whether it contains a transparent attribute, if the transparent attribute exists, the descriptor chain table is directly transmitted to the output comparator through a bypass channel, bypassing the complex calculation link of the reference model; if not, the traditional path is taken to process the reference model. The application provides a differentiated path selection mechanism, changes the data flow direction of the verification platform, and under the condition that the excitation descriptor chain table contains the transparent attribute, the comparison between the excitation descriptor chain table and the to-be-verified execution result can be performed in advance without waiting for the reference model operation, thereby improving the verification efficiency of the to-be-tested design.

The invention discloses a home decoration digital management system, and belongs to the technical field of home decoration management. The system comprises a design verification module, a project execution management module, a client and contract management module and a data tracing module. The design verification module is used for collecting customer demands and generating a design scheme and scene simulation data confirmed by a customer; the project execution management module executes a construction plan and quality control based on the confirmed scheme; the client and contract management module stores client information and manages a payment process; and the data tracing module records whole-process data from demand acquisition to project acceptance. According to the invention, through constructing full-process digital closed-loop management, it can be ensured that the decoration effect accords with the customer expectation from the source, the problems of delivery disputes and difficult collection of tail money caused by design inconformity are effectively solved, and the construction quality and project management efficiency are improved at the same time.

The invention discloses a mold order conversion method, system and equipment based on 3D printing iterative verification, and the method comprises the steps: receiving a 3D model file and manufacturable information which comprises a material type and a tolerance requirement; 3D printing equipment is dispatched for sample manufacturing; the modified 3D model is received, and 3D printing equipment is scheduled for sample manufacturing; user confirmation information is received, and a 3D model file capable of being used for mold opening is determined; and generating a mold development demand specification containing the 3D model file and the manufacturable information. A full-digital chain of sample verification, data setting and mold order is broken through, and seamless connection and traceability of data streams are ensured. According to the method, the waiting time of sample manufacturing, the time consumption of version coordination and period delay caused by unsmooth communication are remarkably reduced, the overall development time can be shortened, and rapid conversion from design verification to batch production is realized.

The application provides a chip design verification method, system, electronic equipment and storage medium. The chip design verification method comprises: obtaining a design file of a chip and a design stage corresponding to the design file; selecting a target collaborative verification mode matched with the design stage from multiple collaborative verification modes; wherein the collaborative verification mode comprises a mode of verifying the design file by cooperation between logic simulation verification and formal verification; the collaborative verification modes corresponding to different design stages are different, and the cooperation modes between logic simulation verification and formal verification in different collaborative verification modes are different; and verifying the design file based on the target collaborative verification mode. The method makes logic simulation verification and formal verification work collaboratively, combines their respective advantages for complementation, so as to improve the efficiency and effectiveness of chip design and verification.

The application provides a Verilog generation verification method and device for a multi-modal circuit design specification, and relates to the technical field of artificial intelligence. The method comprises the following steps: acquiring a circuit code dataset, generating a first group of circuit pictures, using a large language model to perform natural language description, and constructing a multi-modal circuit dataset; a second group of circuit pictures is generated according to Python code, and a multi-modal general dataset is constructed; a multi-modal large language model is fine-tuned and trained; prompt words are customized for different tasks, a plurality of task agents are constructed according to the prompt words and the trained multi-modal large language model; a core interactive agent is designed, and the core interactive agent and the plurality of task agents are used to complete a circuit design, circuit verification and circuit knowledge question and answer task. The application can improve the circuit design verification accuracy and shorten the design verification time.

The application discloses a deep space exploration constellation system integrated simulation verification method and belongs to the technical field of spaceflight digitized simulation verification. The method comprises the following steps: acquiring a constellation system digitized design model; constructing a standardized message bus taking a CSV file as a carrier, and bidirectionally connecting the digitized design model with a plurality of external professional simulation tools; extracting design parameters from the digitized design model and packaging the design parameters into a first CSV file, and transmitting the first CSV file to the external simulation tools; listening to the message bus to acquire a second CSV file output by the external simulation tools, and analyzing simulation result data; automatically writing the simulation result data back to the digitized design model, and triggering automatic updating of corresponding design parameters; repeating the above steps until the simulation result data meets preset verification conditions or optimization targets, and generating a simulation verification report. The application realizes bidirectional closed-loop iteration between a design model and a simulation model, and improves the automation level of constellation system design verification.

The application provides a water network engineering MBD design verification integrated method and system, and belongs to the technical field of intelligent water conservancy engineering design and operation verification. The method comprises the following steps: constructing an MBD design master model; generating a multi-precision model family, establishing a cross-layer parameter mapping relationship; performing model-in-loop verification MIL, software-in-loop verification SIL and hardware-in-loop verification HIL, and calculating a set of operation performance indexes; comparing the set of operation performance indexes with a preset threshold value to form a layered verification result; calculating a sensitivity matrix to identify key design parameters; taking safe zero violation as a constraint condition, optimizing the key design parameters, automatically writing the optimization result back to the MBD design master model, and generating a versioned design package. The application solves the problems in the existing water network engineering design process, such as separation of design and verification, lack of quantitative correlation between design parameters and operation performance, difficulty in effectively writing the optimization result back to the design master model, and lack of unified traceability mechanism in the design iteration process.

The application relates to an automation equipment digital collaborative design and verification method and device and a storage medium, wherein the method comprises the following steps: extracting effective creation instructions of a three-dimensional model creation process; creating a txt file and saving; extracting size key parameters, encapsulating and writing into a three-dimensional model creation class, and creating a callable three-dimensional model creation function; determining optimization index parameters; executing a model creation step, a finite element simulation step, a kinematics simulation step, and a parameter optimization step to realize optimization and update of the optimization index parameters; based on the updated optimization index parameters, re-executing the model creation step, the finite element simulation step, the kinematics simulation step and the parameter optimization step until an iteration termination condition is reached, and obtaining optimal optimization index parameters; and creating an optimized three-dimensional model based on the optimal optimization index parameters. Compared with the prior art, the application has the advantages of high automation degree, high design verification efficiency, better parameter design and the like.

Digital model platform that enables the streamlined creation and management of digital twins and physical twins by leveraging external feedback and artificial intelligence (AI) is disclosed. Methods and systems for a model collaboration platform that facilitate the integration of external feedback, whether from physical, virtual, or human sources, into the streamlined design, validation, verification, certification, assembly, operations, and maintenance processes of complex systems. Updated results are output to those external sources, including physical twins, other digital twins or models and simulations, and / or human users. External feedback includes feedback data from physical prototypes and their environment, virtual prototypes, simulations, and subject-matter experts. Embodiments are directed to integrating external feedback into the assembly and system-level assessment of digital twins, physical twins, digital threads, and the iterative design of constituting digital engineering models, including constructing, maintaining, and improving digital engineering models for the design, validation, verification, certification, operations, and maintenance of complex systems.

Performing transformer-based design verification for coverage closure in processor devices is disclosed herein. In one exemplary embodiment, a processor device trains an online decision transformer (ODT) using initial trajectories based on regression testing of a Design-Under-Test (DUT). The processor device then performs an online learning phase using the ODT by first generating a plurality of new trajectories. For each new trajectory, the processor device uses the ODT to generate a sequence of actions based on maximizing coverage, transmits the sequence of actions to a testbench environment, receives a corresponding sequence of observed states and a corresponding sequence of coverage metrics from the testbench environment, and generates the new trajectory. The processor device identifies a subset of the new trajectories having a final coverage metric that exceeds a coverage threshold, adds the subset to a replay buffer of the ODT, and retrains the ODT using the replay buffer.

The present invention presents a computer-implemented method for automatically identifying and sealing gaps in geometrical or three-dimensional models for simulation. The method involves creating a multi-volume mesh of the model, defining boundaries to distinguish inside and outside regions, and solving the Laplace equation to identify gaps. By adjusting the iso-surface of the equation's primary variable, the gaps are sealed at desired locations. The model is then divided into distinct inner and outer volumes. The process reduces manual intervention, ensures accurate simulation preparation, and allows user interaction for boundary definition and visualization. The invention streamlines model preparation for simulations, enhancing the efficiency and accuracy of design validation across various industries and allowing much more efficient analysis.

The invention provides an ECC error correction IP core design verification implementation method with configurable error correction bits. The method comprises the following steps: receiving error correction bit configuration parameters; generating corresponding ECC error correction matrix data based on the error correction bit configuration parameters; according to the ECC error correction matrix data, automatically generating a hardware design code forming an ECC error correction IP core; synchronously generating a verification code for verifying the ECC error correction IP core based on the error correction bit configuration parameter; and integrating a hardware design code and a verification code to form an ECC error correction IP core design verification environment capable of configuring error correction bits. According to the method, the ECC error correction capability is flexible and configurable, a full-automatic design verification process from parameters to finished products is provided, the development efficiency and quality are greatly improved, code products which are deeply bound with configuration and can be directly used are generated, and the output stability and applicability are ensured.

The application relates to the technical field of early intervention in automotive controller design, and discloses an early intervention method and device for automotive controller design, wherein the method comprises the following steps: converting functional requirement information into model-based partitioning, combining dynamic operation environment parameter vectorization, jointly generating a requirement index, and automatically generating a configuration parameter set and a design baseline file based on the quantized requirement index. The application has the beneficial effect of realizing early design verification and rapid iteration optimization, guaranteeing the design precision of the automotive controller, and improving the design efficiency.

A system and a method for circuit design verification. The system and a method may reuse data generated in a verification iteration of a previous IC layout, thereby skipping one or more respective steps and / or reducing computation in the verification iteration for the current IC layout, thereby reducing the runtime for verifying the current IC layout. The method includes storing first IC layout data for a first IC layout; identifying one or more modifications between the first IC layout and a second IC layout; analyzing the one or more modifications; and based on the analysis of the one or more modifications, performing one or more of skipping a respective step of the plurality of steps, performing less computation for the respective step, or re-performing the respective step.

The invention relates to the technical field of chip verification, and provides a to-be-tested design verification method, device, equipment and medium, and the method comprises the steps: determining a target execution function from at least two execution functions in a verification environment based on management logic and arbitration logic in a C language direct programming interface (DPI)-C processor model; based on the target execution function, calling a homonymy function execution program corresponding to the target execution function from a program library; and verifying the to-be-tested design based on the homonymous function execution program. According to the method, the DPI-C processor model is used for replacing a real processor, the execution program is directly called according to the management logic and the arbitration logic of the DPI-C processor model, verification of the to-be-tested design is achieved, the situation that according to the specification of the execution program of the processor, the simulation speed is increased, and the iteration verification efficiency is improved is avoided.

The application discloses a hardware unit warehousing method and device, electronic equipment and storage medium, and relates to the technical field of computers.The method comprises the following steps: scanning and processing project files of a hardware design project, determining hardware units contained in the hardware design project and hardware unit information of the hardware units; determining the design verification maturity of the hardware units according to the hardware unit information, and setting a warehousing form of the hardware units by using the design verification maturity and the hardware unit information; querying the warehousing form, and judging whether the hardware units have the design verification maturity meeting preset warehousing conditions; if the hardware units have the design verification maturity meeting the preset warehousing conditions, verifying hardware unit files of the hardware units, and judging whether the hardware units pass the verification; if the hardware units pass the verification, adding the hardware unit files and verification information of the hardware units to a hardware unit management library, and updating the warehousing identifier of the hardware units to the warehousing form; and the automatic warehousing of the hardware units can be realized.

The invention provides a configuration verification method and system for a nuclear power plant reactor protection system and a program product, and the method comprises the steps: obtaining a plurality of card configuration configurations and corresponding test cases, and obtaining FPGA card codes of all cards forming the nuclear power plant reactor protection system, and logic function models of all cards; for each group of card configuration, forming a target model of the nuclear power plant reactor protection system by using the FPGA card code of the target card and the logic function model of the non-target card; performing a simulation test on the target model according to the corresponding test case to obtain actual output data; all the actual output data and expected output data obtained through engineering modeling are compared and analyzed, and a verification analysis result is obtained. According to the method, the card codes of all the cards are alternately verified through the multiple card configuration configurations, dynamic replacement operation and cooperation of the logic function model and the FPGA card codes are achieved, and the efficiency and reliability of design verification are improved.

The system of the embodiment is aimed at realizing design automation based on latest policies. A system according to an embodiment includes an acquisition unit, a design unit, and a verification unit. The acquisition unit acquires the latest policy. The design unit automatically performs design on the basis of the policy acquired by the acquisition unit. The verification unit verifies the design generated by the design unit.

The invention provides an instruction verification method and device, equipment and a storage medium, and relates to the technical field of chip design verification, and the method comprises the steps: dividing a to-be-verified instruction according to a preset multi-layer instruction structure, and obtaining at least one instruction block corresponding to the multi-layer instruction structure; the to-be-verified instruction is a composite instruction comprising a plurality of basic instructions; the multi-layer instruction structure is used for representing a basis for dividing instruction blocks from the perspective of instruction functions, and each instruction block has a respective function; randomly generating a first verification instruction block based on the first instruction block, and generating a second verification instruction block based on the first verification instruction block and the second instruction block; wherein the first instruction block is an instruction block having no constraint relation with other instruction blocks, and the second instruction block is constrained by the first instruction block; obtaining a verification instruction based on each verification instruction block corresponding to the at least one instruction block; and verifying the to-be-verified instruction through the verification instruction. And the random efficiency and fairness of instruction verification are improved.

This invention discloses a unified intermediate representation data model and construction method for hardware design, belonging to the field of electronic design automation. The model includes: a unified representation base class; structural relationship graph representation and temporal behavior representation, describing the structural composition and runtime behavior of the design, respectively; formal semantic consistency constraints to ensure semantic consistency between structure and behavior; and a semantic association architecture to establish bidirectional semantic mapping between various scenario representations such as HDL code, schematics, and waveforms and the unified representation base class. The construction method based on this model includes an incremental synchronization process, achieving automatic synchronization after any representation modification through change capture, cross-representation mapping indexing, and change propagation rules. This invention also provides an AI-assisted design method based on this model, improving AI interaction efficiency and the automation level of design verification through multi-dimensional context construction, syntax stripping, incremental interaction protocols, and automatic closed-loop verification.