98 results about "Design Validation" patented technology

A digital model platform that enables the streamlined creation and management of digital twins and physical twins by leveraging external feedback and artificial intelligence (Al) is disclosed. Methods and systems for a model collaboration platform that facilitate the integration of external feedback, whether from physical, virtual, or human sources, into the streamlined design, validation, verification, certification, assembly, operations, and maintenance processes of complex systems. Updated results are output to those external sources, including physical twins, other digital twins or models and simulations, and / or human users. External feedback includes feedback data from physical prototypes and their environment, virtual prototypes, simulations, and subject-matter experts. Embodiments are directed to integrating external feedback into the assembly and system-level assessment of digital twins, physical twins, digital threads, and the iterative design of constituting digital engineering models, including constructing, maintaining, and improving digital engineering models for the design, validation, verification, certification, operations, and maintenance of complex systems.

The invention provides a DFT test task management method and device, electronic equipment and a storage medium, and belongs to the technical field of chip design verifier.The DFT test task management method comprises the steps that a data model is constructed on the basis of a design module list and a test step list, the data model is used for indicating testability design DFT test steps of all design modules, and the test steps of all the design modules are stored in the test step list; the data model comprises a plurality of DFT test tasks, attributes of each DFT test task comprise a selection state, and the selection state comprises a selected state and a non-selected state; based on the interactive input, determining at least one DFT test task of which the selection state is selected as an executable DFT regression object; and according to the DFT regression object, driving a DFT test task to be executed. According to the method, the DFT test tasks are normalized through the data model, only the DFT test tasks need to be selected for making the test plan, efficient management of the DFT test tasks is achieved, and the regression test efficiency is improved.

Digital model platform that enables the streamlined creation and management of digital twins and physical twins by leveraging external feedback and artificial intelligence (AI) is disclosed. Methods and systems for a model collaboration platform that facilitate the integration of external feedback, whether from physical, virtual, or human sources, into the streamlined design, validation, verification, certification, assembly, operations, and maintenance processes of complex systems. Updated results are output to those external sources, including physical twins, other digital twins or models and simulations, and / or human users. External feedback includes feedback data from physical prototypes and their environment, virtual prototypes, simulations, and subject-matter experts. Embodiments are directed to integrating external feedback into the assembly and system-level assessment of digital twins, physical twins, digital threads, and the iterative design of constituting digital engineering models, including constructing, maintaining, and improving digital engineering models for the design, validation, verification, certification, operations, and maintenance of complex systems.

The embodiment of the invention relates to the technical field of simulation, in particular to an electro-hydrogen chemical coupling system planning design verification method and platform, and the method comprises the steps: building an electro-hydrogen chemical coupling system model, setting configuration parameters and a planning target for the coupling system model, and determining and executing a target planning algorithm according to the planning target to obtain a planning result, determining simulation parameters for the coupling system model according to the indication of the planning result; operating the coupling system model according to the simulation parameters to perform production simulation to obtain a corresponding production simulation result and simulation data of a plurality of equipment simulation models in the coupling system model in the simulation process; optimizing the simulation parameters according to the simulation data to obtain optimized simulation parameters, and operating the coupling system model again according to the optimized simulation parameters to perform production simulation to obtain an optimized production simulation result; and comparing the production simulation result with the optimized production simulation result, and selecting a target planning result. According to the scheme, energy conservation and consumption reduction can be realized, and the system operation stability is enhanced.

The embodiment of the invention provides a chip design verification method and a related device. The chip design verification method comprises the steps of obtaining a to-be-tested chip design and executing the to-be-tested chip design; in the process of executing the to-be-tested chip design, when it is detected that a current transaction processed by the to-be-tested chip design generates blocking delay due to input blocking conditions, if it is determined that the blocking delay exceeds the upper limit of the preset blocking period number, the blocking delay caused by the input blocking conditions is relieved, and the current transaction continues to be processed; in the process of continuing to process the current transaction, if it is detected that the current transaction generates transaction processing delay due to a non-input blocking condition and it is determined that the transaction processing delay exceeds a preset delay upper limit, an error indication is returned; wherein the transaction processing delay is the time difference between the moment when the starting signal of the current transaction is valid and the moment when the completion signal is valid. Through transaction processing delay detection, omission of scenes with problems in the chip can be avoided, and comprehensiveness of problem detection is enhanced.

The invention relates to an engineering construction stage user multi-dimensional demand analysis system and method, and the system comprises a multi-modal semantic model construction module which integrates a multi-source knowledge base, and extracts triple description statements from the provisions of the multi-source knowledge base to construct an engineering object ontology knowledge graph; the demand structured guidance and intelligent analysis engine module dynamically identifies an engineering stage and a user role, guides a user to perform text demand input, and performs semantic completion and standardization processing; the demand conflict detection and coordination correction module is used for detecting conflicts in user demands and generating a conflict influence analysis report and a coordination processing scheme; the intelligent drawing and dynamic optimization module is used for automatically drawing according to the triple obtained through demand analysis; and the demand analysis visualization and flow closed-loop module is used for generating an executable parameterized demand document and an association chart, and completing demand-design-verification engineering closed-loop management, so that intelligent analysis and standardization of user multi-dimensional demands are realized, and the system has the advantages of high efficiency, accuracy and intelligence.

The invention relates to a register design verification file generation method, which comprises the following steps of: performing deep analysis and detailed processing by acquiring structured register description information and applying a built-in LR (Local Register) syntactic analyzer with context-dependent dynamic analysis capability; according to the method, accurate and consistent RTL design codes, RAL verification models and register description documents can be automatically and synchronously generated, the automation level and quality of register related work are effectively improved, the chip design verification period is shortened, the risk that errors are introduced due to information inconsistency is reduced, and human input is saved.

The invention relates to the technical field of chip design verification, in particular to a signal searching system, which comprises an application end, M clients, a processor and a memory in which a computer program is stored, and when the computer program is executed by the processor, the following steps are realized: when the application end executes a task of searching a target signal in a database file, M is a positive integer, and M is a positive integer; a search range corresponding to a database file is cut into M sub-ranges, a task and the corresponding sub-range are sent to a client, the client searches a target signal in the database file according to the corresponding sub-range to obtain a search result, the search result is sent to an application end, and the application end displays all the received search results. According to the technical scheme, the signal searching task is executed in a distributed mode through the multiple clients and then is returned to the application side, the searching efficiency is effectively improved, and then the use fluency of the EDA tool is improved.

To provide a structural design device that reduces a calculation load in optimization calculation for a structural design process.SOLUTION: A structural design device includes: a cross-section information generation unit that generates cross-section information for a structure of a design object; a determination unit that determines whether or not a structure having the generated cross-section information satisfies a condition of a preset evaluation item; and an optimum solution determination unit that evaluates, after the determination by the determination unit is completed, a preset object function and determines an optimum solution for the cross-section information. The evaluation item consists of a design verification item for the structure and a prior-evaluation item that should be considered when designing the structure. The determination unit sequentially determines whether the evaluation items are satisfied and completes the determination when it determines that the evaluation item is not satisfied.SELECTED DRAWING: Figure 1

A method for generating a compliance report that includes receiving, by a report generator, a technical plan and a compliance constraint, processing the technical plan and the compliance constraint, generating the compliance report based on the processing, and providing the compliance report to a user.

A computing system (101) implementing a design verification system (300) to alter (401) a circuit design (301) describing an electronic system into a simplified representation of the circuit design (313), and also implement an analog simulator (340) to perform (402) a simulation of the simplified representation of the circuit design. The design verification system can identify (403) circuit activity (317) corresponding to the electronic system in different temporal windows during the simulation of the simplified representation of the circuit design, perform (404) a topological analysis of the circuit design based, at least in part, on the identified circuit activity in the different temporal windows. The design verification system can modify (405) the circuit design into a plurality of circuit design subsets corresponding to the different temporal windows based, at least in part, on the topological analysis.

The invention discloses an efficient and reliable software and hardware collaborative testing method based on FPGA-PCIe, and aims at solving the problems that an existing testing method is low in efficiency and insufficient in reliability. The method is achieved through the following steps that hardware codes are compiled through Quartus software, and a bin file is generated; burning the bin file to an FPGA (Field Programmable Gate Array) development board; installing a kernel driver and a dependency library; the FPGA is bound through a vfio driver; software codes initialize queues, process interrupts and generate and verify messages, and the specific process comprises the steps of calculating message verification values through hardware, generating and receiving efficient interaction of the messages through software, and ensuring the integrity of data packets. Through deep combination of software and hardware, the flexibility, reliability and efficiency of testing are improved, the method is suitable for testing of a high-speed data interaction scene, particularly has remarkable advantages in FPGA design verification and system-level application, and supports rapid development and deployment of a complex system.

The invention provides a chip design verification method and system, electronic equipment and a storage medium. The chip design verification method comprises the following steps: acquiring a design file of a chip and a design stage corresponding to the design file; selecting a target collaborative verification mode matched with the design stage from a plurality of collaborative verification modes; wherein the cooperative verification mode comprises a mode for verifying the design file through cooperation between logic simulation verification and form verification; the collaborative verification modes corresponding to different design stages are different, and the collaborative modes between logic simulation verification and form verification in the different collaborative verification modes are different; and verifying the design file based on the target collaborative verification mode. According to the method, logic simulation verification and formal verification work cooperatively, and respective advantages are combined for complementation, so that the efficiency and effectiveness of chip design and verification are improved.

Systems and methods are provided for design validation using a validation computing device and a designer computing device. The validation computing device can be configured to obtain a dataset and a record of designer interactions, provide a validation interface, and update a record of reviewer interactions. The validation interface can include a design option indicator, a justification indicator, a visualization display, and a validation control. The reviewer interactions can include rejecting a modification of a design option. The designer computing device can be configured to obtain the record of reviewer interactions; display the rejection of the modification; and provide a design interface for revising the modification or revising a justification of the modification.

The invention discloses an MBSE-based material allocation and transportation system forward design method, which comprises the following steps of: dividing an overall design process into four levels, namely an overall task layer, a system layer, a subsystem layer and a design verification layer, respectively carrying out material allocation and transportation system design from four dimensions, namely requirements, behaviors, structures and parameters, constructing a requirement model, a function model and a performance model, and designing a material allocation and transportation system according to the requirement model, the function model and the performance model. Gradually forming a system scheme, and performing rapid simulation verification on the system scheme; wherein the overall task layer pays attention to a top-layer functional architecture and a system context environment of the material allocation and transportation system, and a preliminary scheme of the system is formed; the system layer deeply studies the functional architecture, the logic architecture and the performance indexes of the material dispatching system to form a detailed scheme of the system; the subsystem layer carries out the design of the demands, behaviors, structures and parameters of subsystems based on the functions, composition and performance indexes of the material allocation and transportation system, and forms subsystem schemes. And the design verification layer verifies the rationality of the design scheme. The design quality and the design efficiency are improved.

The invention provides a multi-modal knowledge graph generation method and system for hardware design analysis, which break through design, verification and physics, realize information barriers among the three traditional EDA (Electronic Design Automation) fields, perform semantic fusion and association on information from different data fields, create a unified and queriable hardware design knowledge representation, and improve the reliability of hardware design analysis. And a coherent and operable unified knowledge model is formed. A multi-modal design knowledge graph is created by integrating a simulation result (dynamic data) and a physical implementation feature (performance data) into a static structure model, and a comprehensive design model with structure, behavior and performance features is analyzed in a unified framework. An engineer does not need to manually switch between different tools and data formats, but can access all-dimensional information about a static structure, a dynamic behavior and a physical property of a design through a single query interface.

The invention relates to a CAD model generation system and method based on natural language modeling. The CAD model generation system comprises a data layer, an application layer and a middle layer. The application layer is used for acquiring request information of a user; the middle layer is used for analyzing the request information through a natural language processing method to obtain parameters corresponding to the design intention of the user; mapping the corresponding parameters of the user design intention to a predefined structure template, and associating a standard; according to the structure template and the constraint condition, generating an automatic script for constructing a two-dimensional / three-dimensional model through a depth model generation method; based on the automatic script, adopting Siemens NX software to generate a CAD (Computer Aided Design) model; the data layer is used for querying corresponding standard terms in a knowledge base according to the association standard; and based on the standard terms, extracting constraint conditions corresponding to the association standards. The method is suitable for rapid modeling and design verification of complex parts in a weapon system.

The invention relates to the technical field of chip design verification, in particular to a monitor-based request analysis system, which is characterized in that a monitor is deployed on a key path to obtain transmission information in a case simulation process, and the transmission information is stored in a target file; according to the method, the request and the return of the cache unit can be formatted and stored in an information transmission manner, so that the specific request can be searched and extracted directly according to the target file subsequently, error analysis can be carried out only for the specific request, and the request analysis efficiency of the cache unit is effectively improved.

This application provides an instruction verification method, apparatus, device, and storage medium, relating to the field of chip design verification technology. The method includes: dividing the instruction to be verified according to a preset multi-layer instruction structure to obtain at least one instruction block corresponding to the multi-layer instruction structure; the instruction to be verified is a composite instruction including multiple basic instructions; the multi-layer instruction structure is used to characterize the basis for dividing the instruction blocks from the perspective of instruction function, and each instruction block has its own function; randomly generating a first verification instruction block based on a first instruction block, and generating a second verification instruction block based on the first verification instruction block and a second instruction block; wherein the first instruction block is an instruction block without constraints on other instruction blocks, and the second instruction block is constrained by the first instruction block; obtaining verification instructions based on each verification instruction block corresponding to at least one instruction block; and verifying the instruction to be verified using the verification instructions. This improves the random efficiency and fairness of instruction verification.

The invention provides a research and development verification test management method and system, a computer and a storage medium. The method comprises the following steps: step S110, receiving a preliminary design verification test plan subdivided according to a development plan; s120, information setting is carried out on the received preliminary design verification test plan, a design verification test plan is formed, and the set information comprises plan starting time and plan finishing time; step S130, according to the information set in the previous step, assigning the design verification test plan to the use side client of the corresponding laboratory personnel; step S140, acquiring actual time data information of an actual test performed on the design verification test plan by laboratory personnel; and S150, by designing and verifying the test plan and the actual time data information of the actual test, performing assessment and management according to a preset assessment rule. The method can adapt to various complex verification working conditions, the test efficiency is improved, necessary index calculation results are provided, the labor cost is reduced, and the accuracy is improved.

The invention discloses an instant simulation method of a design end, which belongs to the technical field of design simulation of a certain type of aircrafts, and comprises the following steps: S1, selecting a simulation object, S2, analyzing data correlation, S3, marking and summarizing the simulation object, S4, generating a simulation data template and filling and importing the simulation data template by a user, S5, setting a step length and starting simulation, and S6, gradually simulating. The real-time simulation capability is integrated at the design end, design and simulation integration is achieved, the problem of low efficiency caused by separation of design and simulation in a traditional process is effectively solved, the fixed-version data is obtained and verified in real time, the consistency of full-link data is ensured, simulation result distortion is avoided, and meanwhile, the design efficiency is improved. A direct assignment mode provided by the system enables designers to rapidly and flexibly assign variables in a complex logic expression, design verification and an iteration period are greatly accelerated, in addition, a complete simulation process record and a template reuse function support a rapid regression test, and the simulation working efficiency and the knowledge reuse value are remarkably improved.

The invention relates to a product development process management method and system, and the method comprises the steps: obtaining demand information, carrying out the project creation stage review of the demand information, and determining whether to carry out project establishment or not according to a project creation review result, so as to generate a corresponding project establishment project; performing product design development review on the project approval project, and determining whether to perform a proofing application or not according to a design development review result so as to generate a corresponding sample; performing engineering verification test stage review on the sample, and determining whether to apply for mold opening according to a verification test review result so as to generate corresponding part data; performing design verification test stage review on the part data, and determining whether to perform trial production verification according to a design verification review result so as to generate corresponding trial production verification data; and carrying out production verification stage summarization on the trial production verification data, and determining whether to carry out mass production according to a summarization result of the production verification stage summarization so as to generate a corresponding product. The method has the effect of improving the product development efficiency.

The invention provides a method for semiconductor design verification, a database system and related products thereof. The method comprises the following steps: identifying layout fragments with violation errors in a semiconductor layout verification process and determining fragment information of the layout fragments; performing pattern classification on the layout fragment by utilizing geometric clustering so as to determine a pattern category of the layout fragment; the mode category and the fragment information are stored in a database in an associated mode; extracting the fragment information from the database according to the mode category; and assembling the layout segments into a test matrix based on the segment information for optimizing semiconductor design verification. According to the scheme, the accuracy and efficiency of error detection are effectively improved, and the efficiency and reliability of design verification are enhanced.

The present invention discloses a method for bidirectional association between graphical engineering and code of a spacecraft control system, which includes screening and encapsulating the source code of the simulation verification program, storing the extracted information; using the extracted information to associate with the graphical design project, identifying change items, including addition, deletion, and modification, and automatically updating the graphical design project. The present invention can, based on the existing graphical design project of the spacecraft control system, import the modified simulation verification code, scan and parse it, and can compare the new and old codes, achieving the maximum degree of automatic update of the graphical design project, avoiding repeated modification of the simulation verification program and the graphical design project, and greatly improving the iteration efficiency of the design verification process.

The embodiment of the invention relates to the technical field of reactor testing, in particular to a method for determining the reduction proportion of a simulated reactor core of a simulated reactor relative to an actual reactor core of an actual reactor, the simulated reactor, a design verification and safety checking method of the reactor and a computer storage medium. According to the method for determining the reduction proportion of the simulated reactor core of the simulated reactor relative to the actual reactor core of the actual reactor, the resistance characteristic, the rod bundle heat exchange characteristic and the flow distribution characteristic of the simulated reactor core of the simulated reactor are considered to be similar to those of the actual reactor core of the actual reactor, so that the simulated reactor can meet similar requirements of a natural circulation experiment; the flow heat exchange characteristic of the actual reactor core in natural circulation can be accurately reproduced in a natural circulation experiment; moreover, by determining the proportion of the number of the fuel assemblies of the actual reactor reduced to the number of the fuel assemblies of the simulated reactor, the number of the fuel assembly simulators of the simulated reactor can be greatly reduced under the condition of ensuring the simulation precision, and the experiment cost of the natural circulation experiment is reduced.

The application relates to the technical field of chip design verification, in particular to a request analysis system based on a monitor, which deploys the monitor on a key channel to acquire transmission information in a use case simulation process and stores the transmission information into a target file, so that the request and return of a cache unit can be stored in a transmission information format, the subsequent search and extraction of specific requests can be directly performed according to the target file, and then error analysis can be performed only on specific requests, so that the request analysis efficiency of the cache unit is effectively improved.

The invention relates to an odd number ring violation check optimization method and system based on standard unit adjacent combination, and belongs to the field of integrated circuit physical design verification (DRC) and electronic design automation (EDA). According to the method, all adjacent combinations possibly forming odd rings among standard units are identified in advance before layout, a violation database is established, and a layout tool is guided to avoid using corresponding combinations in the violation database. According to the method, the layout efficiency can be remarkably improved, and later DRC violations are reduced; and through equivalence class merging and symmetric combination merging, a comprehensive violation combination database is provided, a layout tool is guided to make a better decision, and the calculation complexity is greatly reduced.

1. The name of this design product: Test simulation seat (upgraded version). 2. Purpose of this design product: used for corresponding design verification, seat software and hardware test verification and test simulation during the development of the command station. 3. The key point of the design of this product lies in its shape. 4. The picture or photo that best illustrates the design points: three-dimensional picture.

The invention belongs to the field of industrial product research, development, design and verification, and particularly relates to a model-based system virtual integration method. Comprising the steps of performing system design based on a model, including system architecture modeling, component specification definition modeling and component development design modeling; virtual integration test preparation is carried out, a test scheme is planned, and a virtual integration simulation verification environment is constructed; and carrying out model acceptance debugging and virtual integration verification test on model data generated in the system design process. According to the model-based system virtual integration method provided by the invention, a practical and operable method is provided for carrying out system collaborative design verification based on a digital model; according to the method, a model-based system design thought is undertaken, model data generated in the design process is fully utilized, integrated verification is carried out on design work of all parts completed in a labor division mode before development is achieved, design problems are found and solved in advance, and rapid iteration of large-scale complex system design can be promoted.

The application discloses a chip design verification system and method, an electronic device and a storage medium, and relates to the technical field of integrated circuit design. Since the excitation descriptor chain table generated by the dynamic scheduler according to the target test scene can directly present whether it contains a transparent attribute, if the transparent attribute exists, the descriptor chain table is directly transmitted to the output comparator through a bypass channel, bypassing the complex calculation link of the reference model; if not, the traditional path is taken to process the reference model. The application provides a differentiated path selection mechanism, changes the data flow direction of the verification platform, and under the condition that the excitation descriptor chain table contains the transparent attribute, the comparison between the excitation descriptor chain table and the to-be-verified execution result can be performed in advance without waiting for the reference model operation, thereby improving the verification efficiency of the to-be-tested design.