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Late binding of variables during test case generation for hardware and software design verification

a technology of hardware and software design verification and test case generation, applied in the field of design verification, can solve the problems of no longer being generated inputs and the state of the design, and achieve the effects of improving the quality and rapidity of test coverage, reasonable performance penalties, and significantly improving test coverag

Inactive Publication Date: 2006-02-21
IBM CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

[0018]A test generator delays binding of values to variables during generation of test cases until these values are needed by the design. Each variable in the design is associated with a Boolean flag that indicates if the resource has a valid value, or has been evaluated such that its information content is known, or whether its information content is as yet undefined. Each such variable is associated with a linked list that points to other resources that should have the same value. Algorithms are presented, which enable the test generator to handle access to variables with the unidentified values, and deferring binding of the value until it becomes necessary. The technique is powerful enough to handle any arbitrary Boolean function. Experimentally, the late binding technique according to the invention improves the quality and rapidity of test coverage, with a reasonable performance penalty during simulation.
[0022]One aspect of the method includes designating a second unidentified resource for accommodation of a second signal that is a second input of the Boolean function, wherein an output of the Boolean function is insensitive to the second input, and avoiding binding the second unidentified resource with the second signal during execution of the test case.

Problems solved by technology

One problem with the approach of dynamic generation is that in many cases, by the time the generated inputs progress to the area of interest, the state of the design has changed, and the reason that led to the generation of the inputs no longer exists.

Method used

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  • Late binding of variables during test case generation for hardware and software design verification
  • Late binding of variables during test case generation for hardware and software design verification
  • Late binding of variables during test case generation for hardware and software design verification

Examples

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example 1

[0092]The method disclosed with reference to FIG. 3 has been tested using the Odette Verification Environment, details of which are available from the European Electronic Chips & Systems design Initiative, 2 Avenue de Vignate, Parc Equation, 38610 Giéres, France. The Odette Verification Environment provides verification support for object-oriented designs. It is built on top of the SystemC class library, available from Open SystemC Initiative, 1177 Branham Lane #302, San Jose, Calif., 95118-3766. The current prototype has been implemented outside the simulation kernel of SystemC. Therefore, it supports late binding only for a small set of types, namely objects and data-members of objects that are built-in C++ types.

[0093]Reference is now made to FIG. 5, which is a high level block diagram of an I / O device 84, the design of which was verified using the current prototype in order to evaluate the effectiveness of the late binding technique and its ability to improve test coverage. The ...

example 2

[0110]The following pseudocode illustrates one mode of operation of the software verification system 98.

[0111]

input x ... ...Much later first use of xif (x == 87654 ) then {Show it to a user ORShow it to a generator}

[0112]Here the generator is context-aware. It knows that if x is used in a condition, generate values such that in one case x==87654 is true and in another case the condition is false. So with high probability the generator generates x as 87654, which otherwise would have negligible probability. This obviously improves the testing.

[0113]

Second execution.input x ... ...Much later first use of x,  which is different from the first execution.if (x == y ) then   ...   ...

[0114]In the second execution, use of the variable x does not occur in same location in the program as in the first execution, as it depends on other inputs. Assume that y is now 99. The generator will put x=99 with a high probability of correctness, (as the user would).

[0115]The binding of the variable x is...

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Abstract

Methods and systems are provided that improve design verification by test generators by delaying assignment of values in the generated stimuli until these values are used in the design. Late binding allows the generator to have a more accurate view of the state of the design, and in order to choose correct values. Late binding can significantly improve test coverage with a reasonable performance penalty as measured by simulation time.

Description

BACKGROUND OF THE INVENTION[0001]1. Field of the Invention[0002]This invention generally relates to design verification, and more specifically relates to test program generation in a context of a computer mechanism and methods for testing a design for compliance with the design specification.[0003]2. Description of the Related Art[0004]An important aspect of designing a hardware or software design, for example an advanced computer processor, is the ability to test the design of the processor thoroughly, in order to assure that the design complies with desired architectural, performance and design specifications. In current industrial practice, most of the verification is done by generating a very large number of tests by random test generators.[0005]Test program generators are basically sophisticated software engines, which are used to create numerous test cases. By appropriate configuration, it is possible for test generation to be focused on very specific ranges of conditions, or ...

Claims

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Application Information

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Patent Type & Authority Patents(United States)
IPC IPC(8): G01R27/28G06F17/50G06F19/00
CPCG06F17/504G06F17/5022G06F30/3323G06F30/33
Inventor UR, SHMUELZIV, AVI
Owner IBM CORP
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