120 results about "Core set" patented technology

Implementing asymmetric processor cores to enable higher operating frequencies in processor-based devices is disclosed herein. In some aspects, a processor-based device provides a core cluster that comprises a plurality of processor cores and a corresponding phase-locked loop (PLL). Each processor core is based on a common instruction set architecture (ISA) and is configured to operate synchronously based on a same clock signal from the PLL of the core cluster. A first subset of processor cores within the core cluster is implemented with a different physical characteristic relative to a second subset of processor cores within the core cluster, wherein the different physical characteristic enables each processor core of the first subset of processor cores to operate at a higher operating frequency than each processor core of the second subset of processor cores.

A training method, a training device, methods for video decoding and encoding, apparatuses and non-transitory computer-readable storage media thereof are provided. In one training method, a device may collect sample blocks offline, cluster the sample blocks offline into multiple block groups according to attribute information of each sample block, and train a non-separable transform core set offline based on the multiple block groups. The non-separable transform core set comprises multiple non-separable transform cores respectively corresponding to the multiple block groups.

The invention provides a few-sample multi-label Android malicious software detection method based on LLM, and solves the major challenge of keeping stable malicious software detection performance under the condition of data noise and label inconsistency. Two main innovations are introduced into the provided LeoDdroid framework to deal with the challenges. Firstly, a complex core set strategy is realized, representative samples are carefully selected, and the influence of noise is reduced to the maximum extent. Secondly, the advanced reasoning ability of a large language model is utilized through a customized prompt project. In addition, a novel Multi-Sample-ACC measure is introduced, and the measure provides more meaningful evaluation for the multi-label classification performance in the malicious software detection context. The method is characterized in that a consistent MS-ACC (Maximum Sequence-Adaptive Cracking Code) score, which is realized by the LoDandroid on an anonymmouscept data set, a Drebin data set and a VirusShare data set, is higher than 0.93. Due to the powerful framework, the framework is superior to a traditional machine learning method by more than 300% in an anonymmousert data set. These results verify the framework's ability to maintain high detection accuracy with varying degrees of noise and data quality.

Thermal-aware interrupting routing in an interrupt controller in processor-based systems, and related methods are disclosed. The processor-based system includes one or more interrupt controllers that are each configured to prioritize interrupts received from components in the processor-based system and direct each received interrupt to a CPU core(s) in its designated processor to perform an interrupt service routine (ISR) to process the interrupt. To avoid or reduce the likelihood of the interrupt controller directing an interrupt to a CPU core(s) and / or CPU core cluster(s) that may exceed its thermal limit by accepting and handling the interrupt, the interrupt controller is configured to be aware of temperatures of the CPU cores and / or the CPU core clusters in its designated processor. The interrupt controller is configured to selectively route received interrupts based on temperature of the CPU core(s) and / or their CPU core cluster(s) that were determined eligible to receive and handle the interrupt.

Thermal-aware interrupting routing in an interrupt controller in processor-based systems, and related methods are disclosed. The processor-based system includes one or more interrupt controllers that are each configured to prioritize interrupts received from components in the processor-based system and direct each received interrupt to a CPU core(s) in its designated processor to perform an interrupt service routine (ISR) to process the interrupt. To avoid or reduce the likelihood of the interrupt controller directing an interrupt to a CPU core(s) and / or CPU core cluster(s) that may exceed its thermal limit by accepting and handling the interrupt, the interrupt controller is configured to be aware of temperatures of the CPU cores and / or the CPU core clusters in its designated processor. The interrupt controller is configured to selectively route received interrupts based on temperature of the CPU core(s) and / or their CPU core cluster(s) that were determined eligible to receive and handle the interrupt.

The invention belongs to the technical field of artificial intelligence and information retrieval, and particularly relates to a group-level core set selection method for a large model recommendation system. The method comprises the following steps: defining a core set selection task, and taking test loss after minimizing subset fine tuning as an optimization target; the method comprises the following steps: constructing an agent optimization target: based on an optimal transmission theory and gradient norm analysis, considering the distribution difference between a candidate subset and a verification set, and constructing an upper bound of agent test loss; initialization-re-refining calculation: by introducing a special cost matrix, converting an original problem into a p-median problem, and optimizing by using a greedy and sample exchange strategy; and label enhancement: according to a joint distribution category decomposition principle, further improving the category coverage capability and the performance stability of the core set in a label recommendation scene. According to the method, the data scale and computing resource consumption required by fine tuning can be remarkably compressed while the recommendation performance is kept, and key support is provided for efficient deployment of a large language model in a recommendation system.

Performing thermal management based on temperature evolution models in processor devices is disclosed herein. In some aspects, a processor device provides a cluster thermal management circuit that is configured to determine power consumption measurements for corresponding functional units of a processor core of a plurality of processor cores of a core cluster. The cluster thermal management circuit also determines temperature measurements by corresponding digital thermal sensors (thermal sensor) external to a point of interest (POI) within the processor core. The cluster thermal management circuit generates a predicted temperature at the POI based on a temperature evolution model that correlates power consumption measurements and temperature measurements with the predicted temperature at the POI. If the cluster thermal management circuit determines the predicted temperature at the POI exceeds a thermal mitigation threshold, the cluster thermal management circuit performs a thermal management operation.

The invention discloses an EPC full-process technology management method, and the method comprises the following steps: S1, taking a BIM model as a core, integrating geometric data, cost data, progress data and operation and maintenance data, and forming a digital twinborn model; s2, structuring the national standard, the industrial standard and the enterprise construction method into executable rules, and embedding the executable rules into the digital twin model to form a construction specification knowledge graph; s3, collecting construction site data in real time through an IoT sensor network, fusing the construction site data into the digital twinborn model, and driving the digital twinborn model to dynamically update; s4, performing progress prediction, resource optimization and risk early warning through an artificial intelligence AI algorithm based on the dynamically updated digital twinborn model, and outputting a decision instruction; and S5, the acceptance records and quality data of the key processes are stored based on the block chain technology, so that whole-process quality tracing and closed-loop management are realized, and the problems of information isolated island, progress lag, cost increase, quality tracing difficulty and the like in a traditional EPC project are effectively solved.

The invention discloses a dynamic weight-based zero-value adaptive zero-carbon power supply station evaluation method and system, and the method comprises the steps: firstly constructing a multi-dimensional index framework system, and collecting historical data to construct an index core set; dividing two types of data sets, and calculating the subjective weight and reliability of each index; calculating zero-value structure parameters and separating non-zero samples according to the two types of data sets to obtain PCA basic weights, calculating double-cluster fusion entropy and credibility and calibrating objective weights in combination with traditional entropy and missing rate penalty factors, calculating dynamic fusion coefficients and fusing subjective and objective weights based on subjective reliability to obtain final weights, and finally obtaining the final weights of the double-cluster fusion entropies and the credibility of the double-cluster fusion entropies and the credibility of the double-cluster fusion entropies and the credibility of the double-cluster fusion. And performing weighted summation to obtain an index score, and evaluating the power supply station according to the index score. According to the method, the problem of weight distortion caused by zero value interference in a traditional evaluation method is effectively solved through targeted distinguishing processing on zero values, a dynamic adjustment mechanism based on index characteristics is constructed, accurate adaptation of subjective and objective weights is achieved, and the accuracy and robustness of an evaluation result are improved.

The invention provides a task migration method and device, electronic equipment and a storage medium, and the method comprises the steps: obtaining a to-be-migrated task object from a processor core with a task migration demand; obtaining load information and core temperature information of each processor core in a processor core set to which the processor core with the task migration requirement belongs; according to the load information and the core temperature information, inter-core migration is carried out on the task object between the processor cores twice or more, and the range of the inter-core migration comprises the processor cores with task migration requirements. The performance stability of the processor core after receiving the task object is improved, the possibility that the performance of the processor core is abnormal due to the fact that the processor core receives the task object is reduced, the stability of the core temperature of each processor core is improved, and the core temperature control effect of each processor core is optimized.

In an aspect of the disclosure, a method, a computer-readable medium, and an apparatus are provided. The apparatus may be a UE. The UE receives, at a time point, DCI scheduling two or more downlink data channels. The UE receives, within a threshold processing time from the time point, a first control signal in a first CORESET according to a first TCI state. The threshold processing time is allocated for the UE to decode the downlink control information. The UE receives, subsequent to the first CORESET, data according to the first TCI state (a) until an end of the threshold processing time when a second CORESET in which the UE is configured to receive a second control signal does not exist in the threshold processing time or (b) until the second CORESET when the second CORESET exists in the threshold processing time.

Implementing asymmetric processor cores to enable higher operating frequencies in processor-based devices is disclosed herein. In some aspects, a processor-based device provides a core cluster that comprises a plurality of processor cores and a corresponding phase-locked loop (PLL). Each processor core is based on a common instruction set architecture (ISA) and is configured to operate synchronously based on a same clock signal from the PLL of the core cluster. A first subset of processor cores within the core cluster is implemented with a different physical characteristic relative to a second subset of processor cores within the core cluster, wherein the different physical characteristic enables each processor core of the first subset of processor cores to operate at a higher operating frequency than each processor core of the second subset of processor cores.

To provide a prismatic cell that can at least improve the lithium deposition phenomenon. [Solution] A rectangular cell is provided, comprising a housing and two core sets housed within the housing. Each core set comprises at least two cores stacked along a first direction, the outer circumferential surface of each core along the winding direction comprises two planar regions and a first corner region and a second corner region connected to the opposing ends of the two planar regions, respectively, the core adjacent to the housing along the first direction in the core set being the first core, the core adjacent to another core set being the second core, each core set further comprising a first insulating strip, the first insulating strip covering at least a portion of the first corner region of the second core, and one end of the first insulating strip extending through the first corner region of the first core to the first planar region.

The application discloses a hybrid scheduling system of a FaaS platform based on KVM virtualization, which is based on a lightweight user mode scheduling mechanism, and realizes task scheduling and dynamic load balancing through the cooperative work of four core modules, i.e., a pre-execution processor, a task detector, a task distributor and a load balancer. The pre-execution processor analyzes the hybrid execution time of different task types under different scheduling methods, and provides data support for scheduling decisions; the task detector monitors the submitted tasks in the system in real time and judges the task types; the task distributor makes a distribution decision in combination with pre-processing information, task characteristics and real-time load proportion; and the load balancer ensures the load balancing between scheduling sets through real-time load monitoring, and avoids the overload of single-core sets. The application can reduce the average execution time of tasks of the FaaS platform in a high-concurrency scenario, improve the resource utilization rate and task execution efficiency, and provides an efficient and reliable solution for serverless computing task scheduling.

A laminated core set for a rotor, having at least one first laminated core and at least one second laminated core, each having internal toothing for fastening to a rotor shaft and forming a magnet carrier. The magnet carriers have recesses for receiving magnets. A circumferential orientation is a relative position between the recesses and the internal toothing of a laminated core and the circumferential orientation of the first laminated core is different from the circumferential orientation of the second laminated core. A rotor for an electric machine is provided having such a laminated core set and a rotor shaft to which the laminated core set is attached such that the recesses of axially adjacent laminated cores are arranged rotated by a predetermined angular offset.

Method and apparatus for dynamically selecting a super queue size for CPUs with a higher number of cores. An apparatus comprises a plurality of compute modules, each module comprising a plurality of processor cores with integrated first-level (L1) caches and a shared second-level (L2) cache, a plurality of last-level caches (LLCs) or LLC blocks, and a plurality of memory interface blocks connected via a mesh interconnect. A compute module is configured to arbitrate access to the shared L2 cache and enqueue L2 cache misses into a super queue (XQ). The compute module is further configured to dynamically adjust the size of the XQ during runtime operations. The compute module tracks parameters including an L2 miss rate or count and an LLC hit latency and adjusts the XQ size as a function of these parameters.A lookup table using the L2 miss rate / count and LLC hit latency can be implemented to dynamically select the XQ size.

The utility model discloses a kind of automatic core-dropping machines for box molding line, including shell, its inside is provided with integrated suction cup assembly, the integrated suction cup assembly includes sealing plate, the sealing plate is arranged in the inside of shell, the bottom of the sealing plate is fixedly connected with several groups of suction cups, positioning block is fixedly connected on the side wall of one side of sealing plate, integrated suction cup assembly is formed modular assembly structure with shell by sealing plate, cooperate the quick locking design of locking assembly and positioning block, without the aid of tool, the positioning and fixation of integrated suction cup assembly can be completed, when different specifications of suction disc need to be replaced to adapt to different sand core, only need to be removed the constraint of positioning block by locking assembly and positioning rod, integrated suction cup assembly of old can be quickly taken down and new component is installed, greatly simplify replacement operation process, effectively shorten equipment downtime, significantly improve the continuous operation efficiency of production line.

The invention discloses a method and device for cross-edge federated domain incremental learning, a medium and equipment, and the method comprises the steps: screening out a core sample set from first old domain data through employing a core set playback algorithm based on a K center heuristic mode; balancing the learning of the new task knowledge and the retention proportion of the core sample set by adopting a mixed strategy of elastic weight consolidation and progressive knowledge distillation to obtain new domain data and second old domain data after feature balance; based on a cross-domain feature alignment algorithm of maximum mean value difference, minimizing the distribution difference of the new domain data and the second old domain data in the feature space to obtain new domain representation with consistent features; and calculating a model update quantity difference value based on the new domain representation with consistent features and the data of the static equipment in the new edge environment, and performing dynamic weighted aggregation on the new domain representation with consistent features based on the model update quantity difference value to obtain a cross-edge federated domain incremental learning model. According to the method, the problem that old knowledge is forgotten due to the fact that cross-edge equipment enters a new edge system to participate in federal training is solved.

The application provides a core set calculation method for a graph structure, relates to the field of graph structure, and constructs a citation network graph and generates an adjacency vector of each node, calculates a DOPH signature of each adjacency vector, and then performs clustering division based on the DOPH signature, calculates by using a GA error, and accelerates by using a clustering-based method, and meanwhile, the application combines a reverse reachable set of the node, selects the node to form a core set, so that the application constructs the core set capable of representing the information of the whole graph structure based on the propagation characteristics, local structure similarity and global role information of the nodes in the graph. Further, the framework introduces a graph adaptive sampling strategy and an adjustable covering mechanism, can dynamically balance the calculation efficiency and the representation accuracy according to the task requirement, and thus realizes the automatic balance between the effect and the cost.

The invention relates to a multi-core CPU load balancing scheduling method based on dynamic queue migration and electronic equipment, and the method mainly comprises the following steps: firstly, initializing a physical core set, establishing a corresponding virtual machine identification task queue for each physical core, and sorting according to a core number; when a vCPU allocation request of a virtual machine is received, the queue length of each physical core is calculated, and a virtual machine identifier is inserted into a corresponding physical core queue according to a shortest queue priority principle; counting the queue lengths of all physical cores, and calculating the longest queue length and the shortest queue length; judging whether load unevenness (no idle physical core and inconsistent queue length) exists or not, if so, executing differentiated queue rebalance according to length difference, and migrating tasks in a long queue to a short queue; and finally, updating the binding relationship between the vCPU and the physical core to ensure that the load balancing takes effect. Compared with the prior art, the method has the advantages that the computing resources of the virtual machine are distributed fairly, and the physical core utilization rate and the overall system throughput are improved.

This invention discloses an automatic modulation recognition core set selection method based on Forgot Quality Score (FoQuS), belonging to the interdisciplinary field of wireless communication signal processing and deep learning. Addressing the shortcomings of existing methods in automatic modulation recognition tasks, such as neglecting the time-frequency structure and signal-to-noise ratio distribution of signals and using a single evaluation metric, this invention proposes a method that records the prediction trajectories of samples during multiple training rounds, calculates the number of changes in fusion correctness, the number of rounds of persistent errors, and the ratio of accuracy to loss value using the Forgot Quality Score (FoQuS), and dynamically selects a core set based on this score in a hierarchical manner. Retraining the model using the core set significantly reduces the training data size while maintaining recognition performance, demonstrating strong generalization ability and high practical value.

The utility model relates to the technical field of cosmetics, in particular to a core-replaceable cosmetic glass bottle which comprises a rubber base, the upper end of the rubber base is movably connected with a cosmetic glass bottle body in a sleeved mode, and two finger grooves are formed in the outer surface of the cosmetic glass bottle body. The upper end of the cosmetic bottle glass bottle body is fixedly connected with a connecting assembly, and a replacement core set is movably clamped in the connecting assembly. According to the cosmetic glass bottle with the replaceable core, due to the arrangement of the replaceable core set and the connecting assembly, the replaceable core is very convenient to mount and dismount, a consumer can replace the replaceable core conveniently, time and energy are saved, the replaceable core body in the replaceable core set can be replaced independently, and after cosmetics in the replaceable core body are used up, the replaceable core body can be replaced independently. A consumer does not need to discard the whole glass bottle and only needs to purchase a new replacement core group for replacement, so that the waste of glass packaging is greatly reduced, and the resource consumption and the environmental pollution are reduced.

The invention relates to the technical field of computers, in particular to a chip verification method based on multi-core constraint solving, electronic equipment and a medium, and the method comprises the following steps: S1, a main thread obtains a candidate solver core set of a target constraint problem; s2, the main thread obtains M sub-threads; s3, the main thread copies the target constraint problem into M copies and sends the M copies to each Wm, and each Wm executes the target constraint problem in parallel; s4, returning a solving result of the optimal Cm by the main thread, and generating a target solver core set; s5, when the target constraint problem is obtained again, D1 is selected to solve the target constraint problem; s6, monitoring the function coverage rate increasing speed, and if the coverage rate increasing speed meets a preset coverage rate increasing speed reducing condition, executing S7; and S7, selecting a target Di, switching to the target Di to solve the target constraint problem, and returning to execute the step S6. According to the invention, the convergence speed of the chip function coverage rate is improved.

Performing thermal management based on temperature evolution models in processor devices is disclosed herein. In some aspects, a processor device provides a cluster thermal management circuit that is configured to determine power consumption measurements for corresponding functional units of a processor core of a plurality of processor cores of a core cluster. The cluster thermal management circuit also determines temperature measurements by corresponding digital thermal sensors (thermal sensor) external to a point of interest (POI) within the processor core. The cluster thermal management circuit generates a predicted temperature at the POI based on a temperature evolution model that correlates power consumption measurements and temperature measurements with the predicted temperature at the POI. If the cluster thermal management circuit determines the predicted temperature at the POI exceeds a thermal mitigation threshold, the cluster thermal management circuit performs a thermal management operation.

The application provides a spin lock deadlock detection method of a multi-core operating system, and the method comprises the following steps: acquiring an operating system processor core set, and sequentially searching variables of each processor core; removing processor cores without spin lock information to be acquired in the variables to form a to-be-detected core set; using a bitmap dyeing method to cyclically search whether a processor core running a detection program in the to-be-detected core set acquires a spin lock, if yes, a deadlock occurs, if not, the processor core is removed, and other processor cores are sequentially detected until the to-be-detected core set is empty, the multi-core operating system does not have a deadlock, and the detection ends. The method designed by the application has the advantages of high efficiency, accuracy, simplicity and convenience, can detect a deadlock problem as early as possible and timely feedback, and enables a user to take corresponding deadlock release measures according to a feedback result, so that the system can continue to run.

The present invention relates to downlink assignment for a downlink control channel. Disclosed are an apparatus, method, and system for downlink assignment of a downlink control channel. A method includes: receiving at least two downlink control channel candidates, which carry the same downlink control information (DCI) and correspond to a transport block (TB); in response to receiving the at least two downlink control channel candidates, determining an associated core set for reception of the TB; based on the associated core set, determining a physical uplink control channel (PUCCH) resource for the TB; and sending a hybrid automatic repeat request response (HARQ-ACK) corresponding to the TB on the determined PUCCH resource.