The application discloses an optoelectronic
chip layout wiring method, device and equipment and a storage medium, relates to the technical field of optoelectronic
chip layout automatic design wiring, and comprises the following steps: mapping the optoelectronic
chip layout into a grid, mapping the
PCell port of a parameterized unit into a point coordinate, and mapping the
waveguide needing to be wired into a
line segment; taking a cross-shaped grid in the grid as a basic unit, defining the center coordinate of the cross-shaped grid and the
line segment passing through the center coordinate of the cross-shaped grid as variables; setting the path between the
PCell ports, the restriction conditions of points and line segments on the path; using the variables to represent the length of the path, and based on the restriction conditions, calculating the corresponding variable values according to the equal-length path to be implemented, so as to determine the path planning, and finally mapping the path planning into the
waveguide wiring. The application can ensure that the
waveguide lengths are equal during wiring, the number of curved waveguides is equal, and the waveguide occupation area is minimum and the total length of the waveguide is shortest.