The invention provides a
PCELL layout design optimization method and device, a medium and equipment, and is applied to the technical field of
chip design. Flexible
layout drawing is carried out by acquiring the
PCELL containing the process parameters and the graph adjustable parameters, so that the
layout structure parameters of the current
PCELL are obtained. A three-dimensional
device simulation model is constructed by using the parameters, and a
simulation compact model is created by using an
artificial neural network algorithm to describe the electrical behavior of the device. And verifying the
electrical performance trend of the three-dimensional
device simulation model by using the PCELL and the
simulation compact model. And when the
verification is passed, further verifying whether the module test circuit meets a preset PPA index. And if yes, fixing the structural parameters of the current PCELL layout. According to the method, process and design requirements are integrated through a construction and parameterization method, and
simulation and
verification of closed-loop feedback are utilized, so that the design precision and the process maturity are improved, the
development period is shortened, and the reliability and efficiency of the process are enhanced.