Method for achieving quasi-Newton algorithm acceleration based on high-level synthesis of FPGA

A quasi-Newton algorithm and high-level synthesis technology, applied in the field of quasi-Newton algorithm acceleration, can solve problems such as gaps, multi-time analysis and design, and development difficulties, and achieve the effects of good versatility, reduced development difficulty, and improved operating speed

Inactive Publication Date: 2017-05-31
TIANJIN UNIV
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Problems solved by technology

Complicated timing design inside the FPGA generally requires state machine development, which takes a lot of time for analysis and design, and software engineers use high-level languages ​​​​C, C++ for development and hardware engineers use RTL design

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  • Method for achieving quasi-Newton algorithm acceleration based on high-level synthesis of FPGA
  • Method for achieving quasi-Newton algorithm acceleration based on high-level synthesis of FPGA
  • Method for achieving quasi-Newton algorithm acceleration based on high-level synthesis of FPGA

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specific Embodiment

[0029] In the present invention, the objective function module is set as an artificial neural network. According to the above steps (1) to (4), each step will be described in detail below.

[0030] The block diagram of the realization module composition of the quasi-Newton algorithm is as follows: figure 1 As shown, it consists of gradient calculation module (Compute_grad), matrix update module (QN_formula), linear search module (Line_search) and artificial neural network (Object_function). First, the gradient calculation module will output the gradient value according to each training set of the artificial neural network, calculate the search direction based on the initial vector and the gradient value, and then use the golden section method to find the optimal search step size by using the search direction, and calculate the objective function, which is the artificial neural network. The extreme value of the network. The most computationally intensive operation in the matri...

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Abstract

The invention discloses a method for achieving quasi-Newton algorithm acceleration based on high-level synthesis of an FPGA. The method comprises the steps that 1, functions of a quasi-Newton algorithm are analyzed, and main calculation modules of the quasi-Newton algorithm are divided; 2, advanced languages C and C++ are utilized to achieve modules in the step 1, and the correctness of the functions of the algorithm are verified; 3, the quasi-Newton algorithm with the functions correct through function verification in the step 2 serves as an input file, a high-level synthesis tool is utilized to convert the advanced languages into RTL-level languages, and generated RTL codes are verified; 4, the generated RTL codes are manufactured into bitstream files, and the files are downloaded to the configurable logical parts of the FPGA. Starting from the quasi-Newton algorithm acceleration, high-level synthesis is utilized to achieve the quasi-Newton algorithm, quasi-Newton algorithm acceleration is achieved through the FPGA, and the FPGA development difficulty is reduced.

Description

technical field [0001] The present invention relates to a quasi-Newton algorithm (Quasi-Newton, QN) acceleration technology, in particular to a high-level synthesis (High Level Synthesis, HLS) tool optimization acceleration quasi-Newton algorithm based on field programmable gate arrays (Field Programmable Gate Arrays, FPGA) Methods. Background technique [0002] The quasi-Newton algorithm is the most effective method for solving nonlinear optimization, and it is widely used in various fields, such as stochastic optimization, integrated circuit layout and loading frequency control of power systems. A critical factor for these applications is obtaining an optimal solution within a limited time. However, the quasi-Newton algorithm takes a lot of time because it contains a large number of iterative algorithms. Therefore, the acceleration of the quasi-Newton algorithm is an important research direction. [0003] With the rapid development of FPGA, the current FPGA platform has...

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Application Information

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IPC IPC(8): G06F9/45
CPCG06F8/443G06F8/441
Inventor 刘强马磊
Owner TIANJIN UNIV
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