FPGA for high-capacity data and opencl-based FPGA algorithm

Abstract

The invention provides an FPGA for high-capacity data and an opencl-based FPGA algorithm, and belongs to the technical field of data calculation. The FPGA comprises an FPGA controller, a pcie interface in instruction communication with the FPGA controller, a Flash controller, a DDR controller and an algorithm module, and also comprises a Flash memory controlled by the Flash controller and a DDR memory controlled by the DDR controller. The Flash controller is in instruction communication with the DDR controller, and the DDR controller is in instruction communication with the algorithm module; the data transmission is carried out between the pcie interface and the Flash controller, the data transmission is carried out between the Flash controller and the DDR controller, and the data transmission is carried out between the DDR controller and the algorithm module. According to the method, the Flash controller and the Flash memory are arranged on an original FPGA, so that a large amount ofto-be-calculated data is moved to the Flash memory at one time by the host through the pcie interface, and then each piece of to-be-calculated data is moved to the DDR memory, so that the situation that the data is moved through the pcie interface for multiple times is avoided, and the algorithm acceleration effect is realized.

Description

technical field [0001] The invention belongs to the technical field of data calculation, and in particular relates to an FPGA for large-capacity data and an FPGA algorithm based on opencl. Background technique [0002] In the current opencl-based algorithm architecture, the host moves data to the DDR plugged into the FPGA through the pcie interface. The kernel algorithm module takes out the data from the DDR, performs algorithmic logic operations, and then sends the calculated data back to the DDR, and then the host takes the calculated data from the DDR through the pcie interface. In this prior art, due to the use of DDR as a cache, the storage resources are limited, and the hardware of DDR is more complicated, increasing the number of DDRs requires higher hardware requirements for FPGA, and because each time the host sends and receives data, the pcie interface link consumes The time resource is relatively large, which reduces the usage rate of the kernel algorithm module ...

AI Technical Summary

Problems solved by technology

In this prior art, due to the use of DDR as a cache, the storage resources are limited, and the hardware of DDR is more complicated, increasing the number of DDRs requires higher hardware requirements for FPGA, and because each time the host sends and receives data, the pcie interface link consumes The time resource is relatively large, which reduces the utilization rate of the kernel algorithm module per unit time and limits the performance of the algorithm

For algorithms that require large capacity such as neural network algorithms, image processing algorithms, etc., the above technologies cannot perform algorithmic calculations quickly

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