64 bit floating-point integer amalgamated arithmetic group capable of supporting local register and conditional execution

A technology of conditional execution and floating-point integers, which is applied to general-purpose stored-program computers and architectures with multiple processing units. The effect of width

Inactive Publication Date: 2007-08-22
NAT UNIV OF DEFENSE TECH
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

However, there are many difficulties in the design of 64-bit arithmetic groups

Method used

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  • 64 bit floating-point integer amalgamated arithmetic group capable of supporting local register and conditional execution
  • 64 bit floating-point integer amalgamated arithmetic group capable of supporting local register and conditional execution
  • 64 bit floating-point integer amalgamated arithmetic group capable of supporting local register and conditional execution

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Embodiment Construction

[0021] The present invention will be described in further detail below in conjunction with the accompanying drawings and specific embodiments.

[0022] A 64-bit floating-point integer fusion operation group supporting local registration and conditional execution of the present invention, which includes one or more 64-bit floating-point / integer fusion operation components, used to solve control-related conditional execution components, used for The component interconnection structure and controller that realize data cross-sharing. The entire LRF address space is composed of several completely independent address spaces. One input of each computing component corresponds to one address space. All computing groups cannot directly address it. Local The operation group can only perform indirect addressing access to each address space through the unified controller; the controller has a special instruction memory to store the compiled instructions, and when the program is executed, th...

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Abstract

The invention discloses a 64-bit floating-point integer-fusion operation group which support partial deposit and conditional execution. It includes one or more 64-bit floating point / integer-fusion arithmetic unit, conditional execution unit, component interconnect structure and control unit. The computing unit is connected with conditional execution unit by interconnect structure which also is used to transfer data among units. The storage address of operation group is made up of several independent address spaces, and the local operations can indirectly visiting each address space by unified controller. There are specialized instruction register to storage compiled order. The controller send the compiled instruction to each function unit of the corresponded computing group at the same time when the program running, then each group receive instructions and run it by SIMD and storage the result in the same LRF or output.

Description

technical field [0001] The present invention mainly relates to the field of design method of 64-bit floating-point and integer operation group in chip design, in particular to a 64-bit floating-point integer fusion operation group supporting local register and conditional execution. Background technique [0002] With the emergence of a large number of computing-intensive applications, how to effectively use a large amount of data parallelism in the program has become the focus of the computer community. Among many computing-intensive applications, the data parallelism of media streaming is particularly prominent. Such as multimedia, graphics and image processing, and signal processing, all contain a lot of data parallelism. Aiming at this large amount of data parallelism applications, many architectures that can effectively extract this kind of parallelism have been produced, such as vector processors and SIMD processors, etc., and these structures can obtain high performan...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F15/80
Inventor 邢座程蒋江杨学军张民选张明穆长富阳柳曾献君马驰远李勇陈海燕高军李晋文衣晓飞倪晓强唐遇星张承义
Owner NAT UNIV OF DEFENSE TECH
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