88 results about "64-bit computing" patented technology

A processor has multiple operating modes, such as the long/compatibility mode, the long/64-bit mode and the legacy modes of the x86-64 microprocessor. Different software entities execute in different ones of these operating modes. A switching routine is implemented to switch from one operating mode to another and to transfer control from one software entity to another. The software entities may be, for example, a host operating system and a virtual machine monitor. Thus, for example, a virtual computer system may comprise a 64-bit host operating system and a 32-bit virtual machine monitor, executing on an x86-64 microprocessor in long mode and legacy mode, respectively, with the virtual machine monitor supporting an x86 virtual machine. The switching routine may be implemented partially or completely in an identity-mapped memory page. Execution of the switching routine may be initiated by a driver that is installed in the host operating system of a virtual computer system.

The invention relates to a parallel microprocessor and a corresponding realization method which are based on FPGA development. The parallel microprocessor comprises a CPU which is a 32-bit fixed-point CPU formed by a fetch decoding unit, a process management unit and an integer instruction execution unit; a communication module formed by a plurality of units of LINK channels and In/Out controllers; an arbitration controller used for arbitrating internal and external address buses and a data bus of the CPU; an external memory interface used for providing reading/writing time-sequence logic for an external memory; an interruption/time-sequence controller used for providing timing and interruption for the CPU; an internal memory used for providing the instructions of the CPU and quickly accessing data. The CPU is also provided with a floating point unit (FPU) combining the 32-bit fixed-point CPU to form a 64-bit floating point CPU. The 32-bit fixed-point parallel microprocessor and the 64-bit floating point parallel microprocessor provided by the invention work stably, bring convenience for system modification and debugging, accelerate verification speed and provide a low-cost operation platform for programs written in OccamII language.

A method and apparatus for managing shared virtual storage in an information handling system in which each of a plurality of processes managed by an operating system has a virtual address space comprising a range of virtual addresses that are mapped to a corresponding set of real addresses representing addresses in real storage. The virtual address spaces are 64-bit address spaces requiring up to five levels of dynamic address translation (DAT) tables to map their virtual addresses to real addresses. One or more shared ranges of virtual addresses are defined that are mapped for each of a plurality of virtual address spaces to a common set of real addresses. The operating system manages these shared ranges using a system-level DAT table that reference a shared set of DAT tables used by the sharing address spaces for address translation, but is not attached to the hardware address translation facilities or used for address translation. The shared range of virtual addresses straddles the 2⁴²-byte boundary between ranges served by different third-level DAT tables and is situated between a lower private range and an upper private range so that an individual address space can map both a lower private range and a shared range using only three levels of DAT tables. Each shared address range may be shared with either global access rights, in which each participating process has the same access rights, or local access rights in which each participant may have different access rights to the given range. Access rights for each participant may be changed over the lifetime of the process.

In an embodiment, a processor includes a register file having multiple widths corresponding to different operands sizes of a given data type implemented by the processor. For example, the integer register file may have 32 bit and 64 bit widths for 32 and 64 bit operand sizes. The register file may have a section of registers for each operand size, and the map unit may allocate registers from the appropriate section for each instruction operation based on the operand size of that instruction operation. The register file may consume less integrated circuit area than another register file having the same number of registers, all of which are implemented at the largest operand size. In some embodiments, only the register file and the map unit (specifically the free list management logic in the map unit) are changed to implement the multiple-width register file.

An object storage system comprises one or more computer processors or threads that can concurrently access a shared memory, the shared memory comprising an array of equally-sized cells. In one embodiment, each cell is of the size used by the processors to represent a pointer, e.g., 64 bits. Using an algorithm performing only one memory write, and using a hardware-provided transactional operation, such as a compare-and-swap instruction, to implement the memory write, concurrent access is safely accommodated in a lock-free manner.

The dual mode bus bridge accommodates either two 64-bit personal computer interface (PCI) buses or four 32-bit PCI buses. In either case, only a single load is applied to the host bus. The dual mode bridge includes a bridge controller unit connected to a pair of expansion bridge units by respective internal buses. Each expansion bridge unit includes two sets of 64-bit wide queues and buffers. For 32-bit PCI operation, the two sets of queues and buffers are operated in parallel. For 64-bit PCI operation, the two sets of queues and buffers are linked together so as to appear in series to provide a single queue structure having twice the depth of the separate queue structures for a 32-bit mode operation. As such, undue duplication of queue and buffer resources is avoided. Method and apparatus embodiments of the invention are described.

Prior art attempts to provide 32-bit addressing within a 64-bit computing environment lead to other complications. Hardware solutions result in more complicated hardware which, in turn, increases costs and may reduce the functionality of 64-bit computing and significant changes to commercially available 64-bit processors. Alternatively, previous software solutions are computationally expensive, requiring add and subtract routines convert between 32-bit addresses and 64-bit addresses. An additional problem, specific to IBM™ zSeries hardware, is that the only way to provide a heap size larger than 2 GB, even if less than 4 GB, is to employ the 64-bit addressing in combination with a computationally expensive software patch to emulate 32-bit addressing. By contrast, provided by aspects of the present invention there are systems, methods and computer program products for implementing low-cost pointer compression and decompression. In accordance with more specific aspects of the invention, the systems, methods and computer program products for implementing low-cost point compression and decompression can be specifically adapted to compress 64-bit pointers to 32-bit pointers, and conversely convert 32-bit pointers to 64-bit pointers.

One embodiment sets forth a technique for dynamically mapping addresses to banks of a multi-bank memory based on a bank mode. Application programs may be configured to perform read and write a memory accessing different numbers of bits per bank, e.g., 32-bits per bank, 64-bits per bank, or 128-bits per bank. On each clock cycle an access request may be received from one of the application programs and per processing thread addresses of the access request are dynamically mapped based on the bank mode to produce a set of bank addresses. The bank addresses are then used to access the multi-bank memory. Allowing different bank mappings enables each application program to avoid bank conflicts when the memory is accesses compared with using a single bank mapping for all accesses.

As manufacturers of very fast and powerful commodity processors continue to improve the capabilities of their products, it has become practical to emulate the proprietary hardware and operating systems of powerful older computers on platforms built using commodity processors such that the manufacturers of the older computers can provide new systems which allow their customers to continue to use their highly-regarded proprietary legacy software on state-of-the-art new computer systems by emulating the older computer in software that runs on the new systems. In an example of the subject invention, a 64-bit Cobol Virtual Machine instruction provides the capability of adding to or improving the performance of legacy 36-bit Cobol code. Legacy Cobol instructions can be selectively diverted, in the host CPU, to a 64 bit Virtual Machine Implementation. The output legacy and new Cobol code is compiled in a dedicated implementation of the Cobol compiler, and the output of the special purpose compiler is emulated in a special purpose software emulator, separate from the main software emulator that handles the normal 36-bit stream of legacy code.

The invention discloses a 64-bit floating-point integer-fusion operation group which support partial deposit and conditional execution. It includes one or more 64-bit floating point / integer-fusion arithmetic unit, conditional execution unit, component interconnect structure and control unit. The computing unit is connected with conditional execution unit by interconnect structure which also is used to transfer data among units. The storage address of operation group is made up of several independent address spaces, and the local operations can indirectly visiting each address space by unified controller. There are specialized instruction register to storage compiled order. The controller send the compiled instruction to each function unit of the corresponded computing group at the same time when the program running, then each group receive instructions and run it by SIMD and storage the result in the same LRF or output.

A method for node data reporting and instruction issuing based on LoRa Internet of Things comprises the following steps: step S1-1) the LoRa network node reports the data packet to the LoRa gateway according to the self-defined data format; Step S1-2) the LoRa gateway analyzes the data packet according to the self-defined data format, carries out integrity and correctness verification of each field and packet loss detection, and after the checksum detection is passed, a 64-bit LoRa gateway identification code is added into the data packet and sent to the MQTT server through the MQTT protocol;Step S1-3) the MQTT serv parses the data packet according to the self-defined data format, after passing the check and packet loss detection, encrypts all data units of the data packets, and then sends the data packets to the HTTP server through the MQTT protocol; Step S1-4) the HTTP server parses the data packet according to the self-defined data format, after the checksum packet loss detection is passed, decrypts all data units of the data packet, obtains the original data units, and then stores the data of each field of the data packet into the database.

A method and apparatus for a two micro-operation flow using source override. In one embodiment, the method includes the identification of a macro-instruction having one or more streaming single instruction multiple data extension type operands. Once received, the macro-instruction is decoded into a first micro-operation (uOP) and a second uOP. Once decoded, a signal is asserted to disable source operand override logic if the first micro-operation updates a logical destination register that matches a logical source register of the micro-operation. Otherwise, the mutual source override is active and executed by a register alias table (RAT) when uOP with matching logic source and destination register are detected in a same clock cycle. In doing so, macro-instructions having 128-bit operands may be processed using, for example, two uOPs (one for the lower half and one for the upper half) in a 64-bit implementation, while preserving the atomicity of the original instruction.

The invention relates to a 32 bits microprocessor and its instruction set. The microprocessor system comprises an instruction processor, a control component, a fixing point operation a floating-point operation, a register group, a storage interface component and an I/O processor. The entire instruction cycle adapts two state pipelining and is simple in structure. The system is provided with 16 32 bits general registers which hold 4GB storage address space and input output address space. The storage, the I/O processor and the central processor are connected with 64 bits data path. The speed of the processor can be up to 32 bits instruction flow and 32 bits data flow in each clock cycle. The microprocessor system supports 16 bits, 32 bits and 48 bits three instruction formats which are nine kinds and 50 instructions, wherein, the floating-point add, subtract, multiply and divide, fixing-point divide, fixing-point modulus, the conversion between floating-point and fixing-point are all realized by instructions. The instruction is simplified in number but is strong in function, and also has advantages of RISC and CISC.

A microcomputer system memory architecture and method allows the system memory to provide data access at high speeds in a burst mode. The architecture and method utilizes a system memory controller capable of performing the addressing of the system memory. The microprocessor and the system memory communicate via a high speed host bus. The system memory is comprised of multiple 64-bit system memory buses to permit high speed data transfer to the microprocessor in a burst mode without the need for an external cache.

One embodiment of the present invention provides a system that uses an M-bit operating system (OS) kernel to support N-bit user processes. During operation, the system receives an exception. Note that the exception can be any event that needs to be handled by executing OS kernel code. Specifically, the exception can be a hardware interrupt, a software interrupt, an asynchronous interrupt, a synchronous interrupt, a signal, a trap, or a system call. Next, the system handles the exception by first switching the processor to the M-bit mode, and then executing M-bit OS kernel code which is designed to handle the exception. Note that the processor may primarily be designed to operate in the N-bit mode; the M-bit mode may primarily be provided for backward compatibility reasons.

A scaleable microprocessor architecture has an efficient and orthogonal instruction set of 20 basic instructions, and a scaleable program word size from 15 bits up, including but not limited to 16, 24, 32, and 64 bits. As many instructions are packed into a single program word as allowed by the size of a program word. An integral return stack is used for nested subroutine calls and returns. An integral data stack is also used to pass parameters among nested subroutines. The simplified instruction set and the dual stack architecture make it possible to execute all instructions in a single clock cycle from a single phase master clock. Additional instructions can be added to facilitate accessing arrays in memory, for multiplication and division of integers, for real time interrupts, and to support an UART I/O device. This scaleable microprocessor architecture greatly increases code density and processing speed while decreasing significantly silicon area and power consumption. It is most suitable to serve as microprocessor cores in System-on-a-Chip (SOC) integrated circuits.

The invention provides a DMA controller access implementation method for Loongson blade large-memory address devices. A management control module applies for a 256M address space in a memory; when a DMA controller and an address space lower than 32 bits carry out data transmission, data are transmitted according to the conventional DMA transmission mode; when the DMA controller and an address space higher than 32 bits carry out data transmission, the DMA controller sends an access address to an address-parsing module, the address-parsing module parses and then sends the address to an address conversion module, the address conversion module converts the address, and a mapping module carries out memory mapping according to the address converted by the address conversion module to map the address higher than 32 bits into the memory for which the management control module applies in advance. The method effectively solves the problem that a 32-bit Loongson CPU (central processing unit) cannot support memories exceeding the 32-bit address, and thereby the Loongson CPU can use a 64-bit address space at most.

The invention provides an IPv6 address generation method of a virtual host. The method comprises the following steps: S1, a first router sends a first IPv6 address prefix with a length of 32 bits to aforward affix sending device, and the prefix sending device downwards connects a second router with different network domain sizes and a virtual host; S2, the prefix issue device allocates an IPv6 address prefix with a length of N bit to the second router according to the first IPv6 address prefix and the network domain size, and the prefix issue device allocates a second IPv6 address prefix witha length of 64 bits to the virtual host according to the first IPv6 address prefix; 3, the virtual host obtains a symmetrical key from the central server, and encrypts the information of the virtualhost to generate 64 bits after IPv6 address according to the symmetrical key; S4, the 64-bit second IPv6 address prefix and the 64 bits after the IPv6 address are spliced to generate an IPv6 address.Another aspect of the disclosure also provides an electronic device, an IPv6 address generation system, and a computer readable medium.