5 results about "PCI configuration space" patented technology

The invention provides a PXE network card initialization method and device compatible with 64-bit addressing and a medium, and relates to the technical field of network card initialization, and the method comprises the steps: discovering a network card device; reading a PCI configuration space of the network card equipment, obtaining information of an extended ROM base address register, and mapping a network card Option ROM to a memory shadow region; when the access of the memory mapping input and output mode fails, the initialization code performs read-write operation on the hardware register through a self-defined capability structure in a PCI configuration space of the network card equipment; based on the successfully accessed hardware register, network card hardware initialization is completed, and a PXE protocol stack structural body is established in a memory; registering system firmware as PXE starting equipment, and entering a protocol interaction stage with a PXE server; according to the invention, smooth development of a subsequent network boot flow is guaranteed, and the deployment success rate and the system stability in a large-scale batch installation scene are improved.

The invention provides a method for realizing SR-IOV virtual device discovery by jailhome, which belongs to the technical field of virtual device discovery, and comprises the following steps of: enabling an SR-IOV function of PCIe (Peripheral Component Interconnect Express) equipment on a host in a jailhome driver, and generating n VF (Virtual Function) equipment; in the Hypervisor, creating a VF device resource table associated with the PF device of the PCIe network card, and generating VF device information; and controlling the access and the like of the PCI configuration space of the None root client in the Hypervisor by simulating an MMIO (Man Management Input Output) mode. According to the method, the VF equipment can be discovered on a none root client in a physical PCIe equipment discovery mode by using a partition virtual machine tool jailhouse under an armv8 architecture, and furthermore, the unvarnished transmission of SR-IOV virtual equipment can be realized in combination with an msi-x interruption unvarnished transmission method.

The application provides a PXE network card initialization method, device and medium compatible with 64-bit addressing, relates to the technical field of network card initialization, and comprises the following steps: discovering a network card device; reading the PCI configuration space of the network card device, acquiring extended ROM base address register information, and mapping the network card Option ROM to a memory shadow area; when memory mapping input / output mode access fails, the initialization code performs read / write operation on the hardware register through a self-defined capability structure in the PCI configuration space of the network card device; based on the successfully accessed hardware register, network card hardware initialization is completed, and a PXE protocol stack structure body is established in the memory; the system firmware is registered as a PXE starting device, and a protocol interaction stage with a PXE server is entered; and the application guarantees the smooth development of a subsequent network booting process, and improves the deployment success rate and system stability in a large-scale batch deployment environment.

Embodiments of the present disclosure provide a firmware updating method, an apparatus and a data system. The firmware updating method is applied to the first apparatus, the first apparatus contains at least one PCI configuration space for configuring functions for the first apparatus, and the method specifically includes: configuring firmware updating capability in the first PCI configuration space in the at least one PCI configuration space, and updating the first firmware to the first apparatus based on the firmware updating capability.

An apparatus includes a Peripheral Component Interconnect (PCI) configuration space, and a processor. The processor is configured to receive one or more write commands comprising data related to a firmware; based on a firmware updating capability in the PCI configuration space, write the data related to the firmware to a first memory region corresponding to the firmware updating capability; receive an update command; and in response to the update command, update the firmware to a second memory region.