Method for detecting and correcting memory data accuracy under IP multiplexing

An accurate and memory technology, applied in the SoC field, can solve the problems of inability to guarantee data consistency, failure to provide write-back function, insufficient configurability, etc., to increase the parity bit, easy to implement, and high reusability Effect

Active Publication Date: 2020-11-10
58TH RES INST OF CETC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, when the read data verification error occurs, it fails to provide a write-back function, cannot guarantee data consistency, and verification errors will still occur when reading data again
On the other hand, its method of processing data streams is based on the bit width supported by the ECC basic protection unit. When the data width of the peripheral is smaller than the bit width supported by the ECC basic protection unit, the flexibility is reduced. In the processing of different storage spaces, The configurability it provides is relatively insufficient

Method used

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  • Method for detecting and correcting memory data accuracy under IP multiplexing
  • Method for detecting and correcting memory data accuracy under IP multiplexing
  • Method for detecting and correcting memory data accuracy under IP multiplexing

Examples

Experimental program
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Embodiment 1

[0033] The invention provides a method for checking the accuracy of memory data under IP multiplexing, such as figure 1 As shown, a transfer bridge with error detection and correction functions is inserted between the system bus and the memory controller to expand the data bit width of the memory controller and increase the check bit; the transfer bridge provides the storage of the check bit Space, share the address line with the data of the system bus.

[0034] Please keep reading figure 1 The transfer bridge includes a data bus slave, a data bus master, a configuration bus interface, a space configuration module, a check module, a DEBUG module, and a buffer module. The system bus is an on-chip bus, and different SoC systems adopt different on-chip bus protocols. The method of the present invention is applicable to different bus protocols, and only needs to be based on the data bus slave, data bus master, and configuration bus interface. The corresponding protocol is designed to...

Embodiment 2

[0046] See image 3 The method of the present invention is used in a SoC circuit, and externally mounted storage units with different data widths, such as 8bit, 16bit, and 32bit storage units for storing data, and an 8bit checksum storage unit for storing check codes. The CPU or DMA accesses the memory controller through the system bus, and the external memory is accessed by the memory controller. The transfer bridge integrated with the ECC check module communicates with the CPU through the data bus slave and connects with the memory controller through the data bus master. Before using the external storage unit, configure the DEBUG module and space configuration module of the transfer bridge through the software program, such as configuring the storage data width of the space occupied by the 8-bit, 16-bit, and 32-bit storage unit, and configure the storage space that enables the ECC check function , Enable write-back function and interrupt alarm function.

[0047] When the effe...

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PUM

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Abstract

The invention discloses a method for detecting and correcting memory data accuracy under IP multiplexing, and belongs to the technical field of SoC. An adapter bridge with an error correction and detection function is inserted between a system bus and a memory controller and is used for expanding the data bit width of the memory controller and increasing check bits; and a transfer bridge providesa storage space of a check bit and shares an address line with data of a system bus. the effective data width of the system bus and the data bit width of the storage unit are taken as comparison objects, a data processing method under the condition of read operation errors when the effective data of the system bus does not correspond to the data bit width of a storage unit is added, and write-backoperation of the data of the storage unit is added.

Description

Technical field [0001] The present invention relates to the technical field of SoC, in particular to a method for checking the accuracy of memory data under IP multiplexing. Background technique [0002] With the development of integrated circuits, SoC technology has become a design method and means commonly used in VLSI design. SoC technology is based on IP reuse, which can reduce R&D costs and speed up the development cycle. IP multiplexing technology reuses IP to improve design capabilities, reduces the gap between design and manufacturing, and uses silicon-proven IP to reduce design risks and costs. [0003] In some areas, SoC products will enhance their reliability requirements due to considerations of the working environment or product safety features. For example, the flip of a single bit of data in a storage unit may have a certain impact on system software and hardware. Generally, memory units in many CPU cores integrate error detection and correction logic to reduce sy...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F3/06G06F11/10G06F13/16
CPCG06F3/0619G06F3/0658G06F11/1048G06F13/1668
Inventor 王亚军杨亮桂江华董利匡正阳
Owner 58TH RES INST OF CETC
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