The application discloses a cross-
clock domain register synchronization method and device. It relates to the technical field of digital
integrated circuit design. The method comprises the following steps: when the target
clock domain is unavailable, routing the
bus read-write request to a shadow register array driven by a
system clock, and writing a write
transaction log into a log
queue when the write transaction is completed, the write
transaction log comprising a target address, write data and
byte enable; when the target clock domain changes from unavailable to available and the log
queue is not empty, setting the
handshake signal of the
bus interface to invalid, reading the write
transaction log from the log
queue according to the write sequence, and writing the write data into the target register through a
byte mask circuit according to the target address in the write transaction log; when the target clock domain is available and the log queue is empty, routing the
bus read-write request to the target register, and setting the
handshake signal of the
bus interface to valid. The method realizes register access integrity and
sequential consistency in the target clock dynamic change
scenario.