15 results about "Simd architecture" patented technology

The invention discloses an ALU operation fusion processing module and method suitable for a neural network, and the module comprises a control unit which is used for receiving and decoding a machine instruction, managing the execution processes of internal and external circulation and microinstruction circulation, and generating a control signal of each stage of a microinstruction assembly line; the microinstruction buffer area is used for storing a microinstruction sequence pre-generated by the neural network compiler; the register file is used for storing source operands and results of ALU operation; each entry of the register file is composed of a valid bit, a tag bit and a data bit; the ALU computing core adopts an SIMD (Single Instruction Multiple Data) architecture and comprises a plurality of paths of parallel arithmetic logic function units; the Load / Store unit is used for processing data exchange between a register file and a local buffer area; and the data selection interface is used for selecting a data source or a target buffer area according to the storage tag field of the microinstruction. According to the method, the high efficiency and the flexibility of the ALU in the neural network hardware accelerator can be effectively considered.

The invention discloses a buffer area address allocation and SPILL scheduling method under a multi-level cache architecture, which comprises the following steps of: initializing a free block list for each cache type of an NPU (Network Processing Unit), allocating physical address offset for each buffer area in a computational graph, and executing free block merging and dynamic threshold adjustment; detecting a cache space distribution state, and screening an optimal SPILL victim from the candidate buffer area; reconstructing a dependency relationship between the SPILL operation and original buffer area nodes, and updating the calculation graph; an address multiplexing dependency graph is established and maintained, the life cycle overlapping condition of the buffer area is detected, and address multiplexing constraint and buffer area use time sequence constraint are maintained; and carrying out statistics on the extra data carrying amount brought by the SPILL operation, minimizing the data carrying amount except the total amount, and outputting a final cache allocation scheme and an SPILL operation set. According to the method, on the premise that all hardware constraints and execution constraints of the NPU of the SIMD architecture are met, the cache fragmentation degree is remarkably reduced.

The application discloses a kind of compiler automatic debugging method and system for VLIW and SIMD architecture, the method of the application includes the semantic correctness verification for the program to be checked to judge whether the program to be checked exists semantic error relative to source program, if semantic correctness verification finds that there is semantic error, then determine that debugging is not passed, otherwise the physical register verification for the program to be checked to judge whether the program to be checked exists physical register allocation error, if there is physical register allocation error, then determine that debugging is not passed, otherwise determine that debugging is passed;When determining that debugging is not passed, then generate feedback verification report.The application can automatically check the semantic correctness of program in the process of compiling, and provide accurate verification report (including error occurrence position and type etc.) for developer, improve the efficiency of compiler development, reduce the burden of developer.

A point cloud voxelization method and a related apparatus, which are applied to the technical field of point cloud processing. During a hash value calculation process involved in point cloud voxelization, the present application introduces the maximum coordinate value of a voxel space to calculate hash values corresponding to voxel coordinates, such that the numerical ranges of the hash values can be limited, and the hash value calculation process is simplified, thus helping to accelerate a point cloud voxelization process. In addition, the hash value calculation method is applicable to processors of SIMD architectures such as an NPU, such that the present application can be deployed on a heterogeneous computing platform of the NPU; using different computing units of the heterogeneous computing platform can deploy different steps in the point cloud voxelization process on suitable computing units, so as to fully utilize computing resources of the heterogeneous computing platform, thus sufficiently exhibiting the capability of heterogeneous computing platforms and accelerating the implementation of point cloud voxelization.

Automatic Data Routing Module (ARA) for a computer with a "single instruction, multiple data" architecture comprising several elementary processors, each associated with a local memory, the routing module comprising: - An input interface comprising several input buffers, each intended to receive data read from a respective local memory, - An output interface comprising several output buffers, each intended to transmit data to be written to a respective local memory, - For each input buffer, a selector (SEL) configured to select one or more data items contained in the input buffer, - At least one assembler (ASB) configured to group the data selected by at least two selectors (SELs) into an assembly buffer, - a transfer module (MTR) for each assembler.configured to transfer data from the assembler's assembly buffer to at least one output buffer for writing to at least one local memory location.

Automatic Data Routing Module (ARA) for a computer with a "single instruction, multiple data" architecture comprising several elementary processors, each associated with a local memory, the routing module comprising: An input interface comprising several input buffers, each intended to receive data read from a respective local memory; An output interface comprising several output buffers, each intended to transmit data to be written to a respective local memory; For each input buffer, a selector (SEL) configured to select one or more data items contained in the input buffer; At least one assembler (ASB) configured to group the data selected by at least two selectors (SELs) into an assembly buffer; A transfer module (MTR) for each assembler.configured to transfer data from the assembler's assembly buffer to at least one output buffer for writing to at least one local memory location. Figure 3,

The embodiment of the application discloses a focusing method, device, equipment and computer storage medium, the method comprises the following steps: obtaining an initial image shot by a camera; performing accelerated processing on the initial image based on a single instruction multiple data (SIMD) architecture to obtain a target image corresponding to the initial image; performing sharpness comparison and analysis on the target image and a previous frame of target image to obtain a sharpness change trend, and operating a focusing motor according to the sharpness change trend to realize automatic focusing of a device to be focused. In this way, the initial image shot by the camera is processed by using the SIMD architecture, and then the focusing motor is operated according to the obtained sharpness change trend, so that the rapid focusing of the device is realized.

An automatic data routing module for a “single instruction, multiple data” architecture computer includes a plurality of elementary processors each associated with a local memory, the routing module including: an input interface including a plurality of input buffers, each intended to receive data read from a respective local memory; an output interface including a plurality of output buffers, each intended to transmit data to be written to a respective local memory; a selector, for each input buffer, configured to select one or more data items contained in the input buffer; at least one assembler configured to consolidate the data selected by at least two selectors into an assembly buffer; a transfer module for each assembler, configured to transfer the data from the assembly buffer of said assembler to at least one output buffer for writing said data to at least one local memory.

The invention discloses a point cloud voxelization method and a related device, and is applied to the technical field of point cloud processing. In the Hash value calculation process involved in the point cloud voxelization, the maximum coordinate value of the voxel space is introduced to calculate the Hash value corresponding to the voxel coordinate, so that the numerical range of the Hash value can be limited, the Hash value calculation process is simplified, and the point cloud voxelization process is accelerated. Moreover, the Hash value calculation method is suitable for a processor of an SIMD architecture such as NPU, so that the Hash value calculation method can be deployed on an NPU heterogeneous calculation platform, different calculation units of the heterogeneous calculation platform are utilized, different steps in the point cloud voxelization process can be deployed on proper calculation units, calculation resources of the heterogeneous calculation platform are fully utilized, and the calculation efficiency of the point cloud voxelization process is improved. Therefore, the capability of a heterogeneous computing platform is brought into full play, and the realization of point cloud voxelization is accelerated.

The application discloses a data processing method and system applied to a SIMD computing architecture, and the method comprises the following steps: carrying out block division on data to be processed; reading the divided data block from the memory corresponding to the processor into a first-level cache, and using a vectorization instruction to pre-process the data in the data block; using repeat and stride parameters in the vector instruction to replace the loop control statement during non-continuous reading, carrying and other processing operations; generating a mask matrix at the beginning of the computing process and saving the mask matrix in the first-level cache for reuse; loading the pre-processed data block into a zero-level cache; the zero-level cache is a storage space directly accessed by a matrix computing unit in the corresponding SIMD architecture processor; loading the computing result into the first-level cache, and using the vectorization instruction to post-process the result; and writing the post-processed result back into the memory corresponding to the processor. The application can provide higher efficiency of data processing capacity under the SIMD computing architecture.

The invention discloses a minimum cache residence scheduling method for a SIMD (Single Instruction Multiple Data) architecture neural network processor, which comprises the following steps of: under the condition of meeting basic constraints of a graph structure, cache management and hardware resources, executing topological sorting on a calculation graph, and calculating the key path length of each node through a dynamic programming method; constructing a multi-constraint fusion node priority calculation model, respectively calculating priority components of L0 cache constraint, memory perception and a key path, and summing to obtain a node comprehensive priority; an MCBGS algorithm is adopted, schedulable candidate nodes are screened based on a scheduling state quintuple, nodes are selected in a greedy mode according to the comprehensive priority, and the scheduling state is updated in real time; and accumulating Size values of ALLOC nodes according to a scheduling sequence, progressively decreasing Size values of FREE nodes, calculating the cache residence quantity only containing L1 and UB type buffer areas, and generating a node execution sequence enabling the maximum cache residence capacity to be minimum. The problem of cache resource waste or constraint conflict is solved.

The invention discloses an SIMD architecture-oriented neural network processor intra-core scheduling method and system, and belongs to the technical field of processor scheduling. Through a three-level screening mechanism of the node type priority, the time window priority and the memory influence degree priority, in combination with dependency constraint processing and L0 cache mutual exclusion constraint management, a scheduling sequence which meets a topological sequence and has the minimum peak cache residence amount is generated, idle computing power in a chip is effectively utilized, and the resource utilization rate is improved. On the basis, cache allocation and swap-in and swap-out operation are optimized based on a cost-aware strategy, an optimized scheduling sequence containing swap-in and swap-out operation nodes is generated, swap-in and swap-out memory minimization is achieved, and the scheduling efficiency and the resource utilization rate are further improved. In addition, the method further optimizes the swap-in and swap-out position, and further reduces the total operation time of the operator on the premise of ensuring that the data carrying amount except the total amount is not obviously increased.

The invention provides an atomic operation processing method and device, electronic equipment, a computer readable storage medium and a computer program product, and relates to the technical field of chips. The method is applied to an SIMD architecture, and comprises the following steps: determining a plurality of target threads which access the same memory address and execute the same type of atomic operation in a plurality of threads corresponding to the SIMD architecture; wherein the atomic operation accords with a combination law and an exchange law; the operands of the multiple target threads are reduced and merged according to atomic operation, and target operands corresponding to the multiple target threads are obtained; and according to the target operand, executing one atomic operation on the memory addresses corresponding to the plurality of target threads to obtain a final atomic operation result of all threads corresponding to the SIMD architecture. The method can improve the memory access efficiency.

The application discloses an ALU operation fusion processing module and method suitable for a neural network, and the module comprises: a control unit, which is used for receiving and decoding machine instructions, managing the execution flow of inner and outer loops and microinstruction loops, and generating control signals of each stage of a microinstruction pipeline; a microinstruction buffer, which is used for storing a microinstruction sequence generated in advance by a neural network compiler; a register file, which is used for storing source operands and results of ALU operations; each entry of the register file is composed of a valid bit, a tag bit and a data bit; an ALU calculation core, which adopts a SIMD architecture and comprises multiple parallel arithmetic logic function units; a Load / Store unit, which is used for processing data exchange between the register file and a local buffer; and a data selection interface, which is used for selecting a data source or a target buffer according to a storage tag field of a microinstruction. The application can effectively balance the efficiency and flexibility of the ALU unit in a neural network hardware accelerator.

The embodiment of the invention relates to a data processing method and device, equipment, a storage medium and a program product. The method includes ranking a plurality of hash values corresponding to a plurality of tensors, and dividing the ranked plurality of hash values into a plurality of portions. The method further includes sequentially assigning the plurality of portions to the sorted plurality of cores of the processor, and for a portion assigned to a core of the plurality of cores, causing the core to determine a set of location ranges of each non-duplicate hash value of the portion in the sorted plurality of hash values. The method further includes determining a set of non-duplicated tensors of the plurality of tensors based on the plurality of sets of location ranges of the respective non-duplicated hash values each determined by the plurality of cores. Therefore, the efficient tensor deduplication method which is adaptive to the SIMD architecture and can fully utilize the multi-core parallel computing capability is provided.