Multi-standard LDPC encoder circuit base on SIMD architecture

Abstract

The invention provides a multi-standard low density parity check (LDPC) encoder circuit base on a single instruction multiple data (SIMD) architecture. The LDPC encoder circuit comprises an input buffer unit, a master controller, an instruction memory, an intrinsic information memory, a posterior information memory, an external information memory, a parity check and output buffer unit and a processing unit array, wherein the processing unit array is composed of a plurality of concurrent processing units, and the processing unit adopts very large scale integrated circuits (VLSI) hardware architecture. The encoder adopts a novel two-phase message passing (TPMP) decoding algorithm, ensures that the hardware architecture is not limited by a special architecture of a block matrix, and realizes the separation of the hardware architecture and the block LDPC code check matrix architecture. The invention provides a flexible and configurable design circuit of the processing unit, effectively improves the use ratio of the hardware, reduces design area of chips, provides a dedicated and simplified SIMD instruction set which is suitable for various block LDPC codes, realizes the separation of the hardware architecture and the block LDPC code check matrix architecture, and meets the demands of multi-standard communication.

Description

technical field [0001] The invention relates to a decoder circuit, in particular to a multi-standard LDPC decoder circuit based on a SIMD (single instruction multiple data) structure. technical background [0002] In high-speed wireless digital communication systems, LDPC codes (Low Density Parity Check Codes) are an important type of forward error correction codes (Forward Error Correction), and have the decoding performance closest to the Shannon limit. And it has a very high data throughput rate that parallel processing can provide, is widely used in many wireless communication standards, and is expected to become the most important channel error correction code scheme in future wireless communication standards. IEEE 802.11n (WLAN) and IEEE 802.16e (WiMAX) in the field of broadband wireless access, European digital TV satellite transmission standard (DVB-S2) in the field of digital multimedia broadcasting, Chinese digital TV terrestrial transmission standard (DTMB) and su...

AI Technical Summary

Problems solved by technology

However, the above three hardware design methods all have their defects and deficiencies in the direction of multi-standard LDPC decoder design: method ① is only applicable to TPMP algorithm, not suitable for variable code rate and variable code length hardware structure design, and the hardware implementation is The code length increases and becomes more and more complicated; the parallelism of the processing unit in method ② also has defects in realizing the multi-code rate structure, and is limited by the block LDPC code structure; method ③ is suitable for variable Code rate and variable code length hardware design, but its hardware structure lacks flexibility, and there are difficulties in the design of multi-standard LDPC decoders

This kind of scheme is only suitable for the application of a single communication standard, and there are problems that are not conducive to simplifying the circuit design

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