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Multiply-accumulate instruction which adds or subtracts based on a predicate value

A technology of multiplying and accumulating and accumulating data, applied in the field of multiplying and accumulating operations, can solve problems such as affecting performance, and achieve the effects of reducing energy consumption, improving code density, and efficient memory resources

Active Publication Date: 2011-05-11
ARM LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Furthermore, the running accumulated value within the adder unit is typically held in a register of the same size as the input operand, and accordingly, painstaking efforts are made to ensure that the running accumulated value does not overflow or underflow, typically throughout the accumulated Processing requires the use of various estimation and shift type operations, further affecting performance

Method used

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  • Multiply-accumulate instruction which adds or subtracts based on a predicate value
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  • Multiply-accumulate instruction which adds or subtracts based on a predicate value

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Embodiment Construction

[0046] According to an embodiment of the present invention, a predicate multiply accumulate (predicate MAC) instruction is provided. For the scalar version of the instruction intended to be executed on the scalar processing circuit, the instruction takes the first input data element, the second input data element, and the predicate value used to control whether the multiplication addition operation or the multiplication subtraction operation is performed when the instruction is executed For input operands. Optionally, the predicate MAC instruction can also take the initial multiplication accumulation data element (herein also referred to as the initial accumulation data element) as an input operand.

[0047] However, in order to describe an embodiment of the present invention, it will be assumed that the predicate multiply-accumulate instruction is intended to be executed in the SIMD circuit to perform multiple multiply-accumulate operations in parallel. In these embodiments, th...

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Abstract

A data processing apparatus and method for performing multiply-accumulate operations is provided. The data processing apparatus includes data processing circuitry responsive to control signals to perform data processing operations on at least one input data element. Instruction decoder circuitry is responsive to a predicated multiply-accumulate instruction specifying as input operands a first input data element, a second input data element, and a predicate value, to generate control signals to control the data processing circuitry to perform a multiply-accumulate operation by: multiplying said first input data element and said second input data element to produce a multiplication data element; if the predicate value has a first value, producing a result accumulate data element by adding the multiplication data element to an initial accumulate data element; and if the predicate value has a second value, producing the result accumulate data element by subtracting the multiplication data element from the initial accumulate data element.

Description

Technical field [0001] The present invention relates to a device and method for performing multiply and accumulate (MAC) operations. Background technique [0002] Multiply accumulate (MAC) operations are frequently used in data processing systems. The MAC operation can take the form A+B*C or A-B*C. The multiplication operation B*C is typically performed multiple times for different values ​​of B and C, where the result of each multiplication is then added to the running accumulated value A (or subtracted from the running accumulated value A). [0003] A dedicated MAC circuit is usually provided in a data processing system to optimize the performance of back-to-back MAC operations. Such a MAC circuit can be provided in a scalar processing circuit, where a sequence of multiply-accumulate instructions is executed one after another to perform the required multiply-accumulate operation iterations. However, a known method for accelerating the performance of such operations is to adopt...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F9/302
CPCG06F9/3887G06F9/3001G06F9/30036G06F9/30072G06F9/3893G06F9/30101
Inventor D·H·赛姆斯M·维尔德G·拉里
Owner ARM LTD
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