Separable array-based reconfigurable accelerator and realization method thereof

Abstract

The invention provides a separable array-based reconfigurable accelerator and a realization method thereof. The reconfigurable accelerator comprises a scratchpad memory cache area, separable calculation arrays, and a register cache area, wherein the scratchpad memory cache area is used for realizing reuse of data of convolution calculation and sparsity full connection calculation, the separable calculation arrays comprise multiple reconfigurable calculation units and fall into a convolution calculation array and a sparsity full connection calculation array, the register cache area is a storage area formed by multiple registers, and provides input data, weight data and corresponding output results for convolution calculation and sparsity full connection calculation, input data and weight data of convolution calculation are input into the convolution calculation array, the convolution calculation array outputs a convolution calculation result, input data and weight data of the sparsity full connection calculation are input into the sparsity full connection calculation array, and the sparsity full connection calculation array outputs a sparsity full connection calculation result. Characteristics of two neural networks are fused, so that the calculation resource of the chip and the memory bandwidth use ratio are improved.

Description

technical field [0001] The invention relates to neural network accelerator technology, in particular to a reconfigurable accelerator based on a divisible array and its realization method. Background technique [0002] In the past ten years, deep learning (Deep Learning) technology has promoted the rapid development of artificial intelligence technology. Artificial intelligence technology based on deep learning has achieved great success in the fields of image recognition, video analysis, speech recognition and natural semantic understanding. In some scenarios, it even surpasses human intelligence. The deep neural network (DeepNeural Network) based on deep learning is the core technology for realizing intelligent tasks. At this stage, an intelligent task is often composed of multiple deep neural networks. The current mainstream deep neural networks mainly include: deep convolutional network (Deep Convolution Neural Network, CNN), deep full connection network (Deep Full Conne...

AI Technical Summary

Problems solved by technology

In the hybrid neural network, the convolutional network is a computationally intensive network, and one data transmission can participate in dozens (or even hundreds) of convolution operations, so the convolutional network only needs a part of the memory bandwidth to satisfy all computing resources. Demand for data, resulting in low utilization of memory bandwidth

On the contrary, fully connected networks and recursive networks are memory-intensive, and one data transmission only participates in one operation. Therefore, these two networks can only provide data for a part of computing resources by using all the memory bandwidth, resulting in low utilization of computing resources.

[0006] Second, the waste of resources caused by sparse

The fully connected network has a very high degree of sparsity, so the use of sparse computing to accelerate the fully connected network can improve the performance and energy efficiency ratio, but the existing convolution accelerators are not compatible with sparse network computing, resulting in the shortage of computing resources and bandwidth resources. waste at the same time

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