Sparse matrix solving method based on FPGA parallel acceleration

A technology of sparse matrix and lower triangular matrix, which is applied in the field of data processing, can solve the problems of wasting computing resources, low processing efficiency, and inability to perform calculations, and achieve the effect of improving processing efficiency and saving computing resources

Pending Publication Date: 2021-01-15
NAT SUPERCOMPUTING WUXI CENT +2
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Problems solved by technology

[0003] The sparse matrix solution method based on FPGA parallel acceleration provided by the present invention solves the problems of low processing efficiency, waste of computing resources, and even inability to perform calculations in the prior art, thereby realizing highly integrated software and hardware collaborative acceleration and sparse matrix solution Fine-grained parallel pipeline, saving computing resources and improving processing efficiency

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  • Sparse matrix solving method based on FPGA parallel acceleration
  • Sparse matrix solving method based on FPGA parallel acceleration
  • Sparse matrix solving method based on FPGA parallel acceleration

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[0036] It should be noted that, in the case of no conflict, the embodiments in the present application and the features in the embodiments can be combined with each other. It should be noted that the terminology used in the present invention is only for describing specific embodiments, and is not intended to limit the exemplary embodiments according to the present application.

[0037] Such as figure 1 As shown, a method for solving a sparse matrix based on FPGA parallel acceleration provided in Embodiment 1 of the present invention includes several processing units, including:

[0038] S101: Perform LU decomposition on the sparse matrix A to obtain the upper triangular matrix U and the lower triangular matrix L, and the solution of the sparse linear equation system Ax=b is converted into the solution of the linear equation system Ux=y and Ly=b of the upper and lower triangular matrices;

[0039] S102: Take the reciprocal of the diagonal elements of the upper triangular matri...

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Abstract

The invention provides a sparse matrix solving method based on FPGA parallel acceleration. A sparse matrix is decomposed, reciprocals of diagonal elements of a lower triangular matrix are taken, datais segmented and distributed according to a data dependency relationship, the data in each processing unit is arranged, and accurate beat-level hardware resource scheduling is adopted for calculationaccording to an arranged operation sequence. Therefore, highly-fused software and hardware cooperative acceleration and sparse matrix solving fine-grained parallel pipeline is realized, the problems of low processing efficiency, waste of computing resources and even incapability of computing in the prior art are effectively solved, the computing resources are saved, and the processing efficiency is improved.

Description

technical field [0001] The invention relates to the technical field of data processing, in particular to a sparse matrix solution method based on FPGA parallel acceleration. Background technique [0002] In power system simulation, electromagnetic transient simulation is one of the main system simulation applications and a key component for power system safety analysis and operation. In this application, its core algorithm is to solve the large-scale linear equation system Ax=b. At the same time, through the analysis of actual data, it can be seen that the coefficient matrix A in the linear equation system is usually a sparse matrix, and the denseness of a large sparse matrix in a power system is usually less than 1%. If the sparsity of the matrix cannot be effectively utilized, the computer processing Large-scale sparse matrix operations will waste a lot of storage and computing resources on invalid zero elements, resulting in low processing efficiency and slow processing,...

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F17/16G06F17/12G06F9/50
CPCG06F9/5027G06F17/12G06F17/16
Inventor 李猛顾燕卿刘洪锦王晞阳刘首文
Owner NAT SUPERCOMPUTING WUXI CENT
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