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Universal double 2-vote-2 computer architecture and implementation method thereof

An implementation method and computer technology, applied in the direction of computers, digital computer components, calculations, etc., can solve the problems of large system security risks, low efficiency, non-failure reconfiguration, etc., and achieve the effect of improving maintainability and high fault coverage

Pending Publication Date: 2020-12-11
XIAN FLIGHT SELF CONTROL INST OF AVIC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0002] In the field of railway signaling, in order to improve the safety and reliability of train control, a centralized, two-by-two-out-of-two architecture is generally adopted, where "two-by-two" refers to two sets of two-way signals that can operate independently and seamlessly switch between each other. Redundant redundant master / standby system, 2 CPUs of each channel operate independently, and then compare and vote the processing results, if the results are consistent, the output will be normal, if they are inconsistent, a fault will be reported. In this architecture, computing resources are highly concentrated on the CPU module In general, real-time tasks such as data collection, processing, and comparison are all completed by the CPU, and the clock and tasks are synchronized between the redundancy through the handshake circuit or software. The execution cycles of each task in each system are different and cannot be reconfigured. , and the software is tightly coupled with the hardware, the change of the hardware will cause the modification of the software, and at the same time, any partial software modification may cause a large system security risk
In addition, since each processor generally uses its own serial interface or network interface for maintenance and upgrade, each processor needs to form a physical topology connection with the host computer, which is inefficient and cannot meet the requirements of existing products

Method used

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  • Universal double 2-vote-2 computer architecture and implementation method thereof
  • Universal double 2-vote-2 computer architecture and implementation method thereof
  • Universal double 2-vote-2 computer architecture and implementation method thereof

Examples

Experimental program
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Effect test

Embodiment 1

[0031] figure 1 It is a module composition diagram of a two-by-two architecture computer, combined with figure 1 As shown, this embodiment provides a general-purpose two-by-two computer architecture. The computer architecture includes a maintenance board MTN 30 and computer I series and computer II series with the same structure. The computer I series and computer II series pass The ARINC 659 bus is used for data connection with the maintenance board MTN30; the ARINC 659 bus is used for data exchange and data two-out-two comparison between computer series I and computer series II.

[0032] The maintenance board MTN 30 provides upgrade software programs to different CPU modules in the computer architecture, and records faults.

[0033] In this embodiment, the computer I series includes a self-monitoring processor board VCU1 10 and a self-monitoring input and output board DIO1 11; the self-monitoring processor board VCU1 10 is combined with control software to carry out compute...

Embodiment 2

[0044] This embodiment, in combination with the architecture of Embodiment 1, provides a method for implementing a general two-by-two computer architecture. The specific content is as follows:

[0045] In this embodiment, a two-by-two architecture computer is divided into completely identical and independent computer series I and computer series II, wherein the computer series I includes a self-monitoring processor board VCU1 10 and a self-monitoring input and output board DIO1 11 , the computer II system includes a self-monitoring processor board VCU2 20 and a self-monitoring input and output board DIO2 21 . Both VCU1 10 and VCU2 20 can simultaneously receive input information from the relay interface 50 of DIO1 11 and DIO2 21 .

[0046] In the running mode, the self-monitoring input and output boards DIO1 11 and DIO2 21 collect the discrete signal of the relay interface 50 through an independent collection circuit under the action of the BIU synchronous clock.

[0047] As ...

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Abstract

The invention belongs to the technical field of safety critical computers, and provides a universal double 2-vote-2 computer architecture which comprises a maintenance board MTN30, a computer I systemand a computer II system, wherein the computer I system and the computer II system are identical in structure; the computer I system and the computer II system are in data connection with the maintenance board MTN30 through an ARINC 659 bus; the ARINC 659 bus is used for data interaction and data two-out-of-two comparison of the computer I system and the computer II system; the maintenance boardMTN30 provides upgrading software programs for different CPU modules in the computer architecture and records faults; the computer I system comprises a self-monitoring processor board VCU and a self-monitoring input / output board DIO; the self-monitoring processor board VCU is combined with control software to perform computer system integration and logic control; and the self-monitoring input / output board DIO is used for collecting an external switching value and driving an external relay. The method has the advantages of high safety, high reliability, modular reconfiguration, easiness in maintenance and expansion, convenience and quickness in operation and the like, and provide a universal product for a railway signal system.

Description

technical field [0001] The invention belongs to the technical field of safety-critical computers, and in particular relates to a general two-by-two computer architecture and an implementation method thereof. Background technique [0002] In the field of railway signaling, in order to improve the safety and reliability of train control, a centralized, two-by-two-out-of-two architecture is generally adopted, where "two-by-two" refers to two sets of two-way signals that can operate independently and seamlessly switch between each other. Redundant redundant master / standby system, 2 CPUs of each channel operate independently, and then compare and vote the processing results, if the results are consistent, the output will be normal, if they are inconsistent, a fault will be reported. In this architecture, computing resources are highly concentrated on the CPU module In general, real-time tasks such as data collection, processing, and comparison are all completed by the CPU, and th...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F15/163G06F11/30G06F11/20B61L23/00
CPCG06F15/163G06F11/3017G06F11/2035B61L23/00
Inventor 宋阳牛萌颜纪迅马永忠张乐驰忤鹏博
Owner XIAN FLIGHT SELF CONTROL INST OF AVIC
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