42 results about "Processor board" patented technology

The invention discloses a server and a server monitoring method, and relates to the technical field of servers, the server comprises a graphics processor board and a management board, a first connector is additionally arranged on the graphics processor board, the management board independent of the graphics processor board is additionally arranged, and the management board is connected with the graphics processor board through the first connector. The information monitoring device is used for monitoring the running state of the graphics processor board, so that on the basis of not changing the structure of the graphics processor board, comprehensive coverage and quick response of information monitoring of a plurality of computing devices on the graphics processor board are realized, and the problems of untimely and incomplete information monitoring caused by increase of the devices are solved; and the stability and the safety of the graphics processor board are improved.

A data processing apparatus, a processor, a board card, and a data processing method. The data processing apparatus may be comprised by a combined processing apparatus (20), the combined processing apparatus (20) comprising a computing apparatus (201), an interface apparatus (202), a processing apparatus (203) and a storage apparatus (204). The computing apparatus (201) is configured to execute an operation specified by a user, so as to execute deep learning or machine learning calculation. The computing apparatus (201) may interact with the processing apparatus (203) by means of the interface apparatus (202), so as to jointly complete the operation specified by the user. The interface apparatus (202) is used to transmit data and a control instruction between the computing apparatus (201) and the processing apparatus (203). The storage apparatus (204) is used to store data of the computing apparatus (201) and the processing apparatus (203). The data processing apparatus provides a vector computation scheme integrating different types of fine-grained quantization, so that processing can be simplified, and the advantages of a low bit width operation and small memory occupation of a fine-grained quantization format are fully utilized.

The present application discloses a mainboard, a processor board card, and a computing system. The mainboard includes a plurality of interfaces, a first interface of the plurality of interfaces is configured to be connected to the processor board card having a processor circuit, a second interface of the plurality of interfaces is configured to be connected to a non-processor board card, and the first interface and the second interface are connected to each other via a communication circuit; for the mainboard, a connection-centric design idea is adopted, and the processor board card is regarded to have the same status as the non-processor board card; and because no processor circuit is provided, and only the first interface connected to the processor board card needs to be provided, compared with an original mainboard, an area of the board card in the present application is reduced, and the processor board card and other non-processor board cards may be connected to the mainboard in a stacked manner, thereby reducing the required space, reducing the requirements for the space in the device, and improving the running flexibility of the processor board card simultaneously.

A Grid Edge Platform or a processor board may be configured to monitor a utility grid and quickly determine or respond to a fault condition of the utility grid. The GEP may include a data acquisition system configured to acquire data from one or more sensors of the utility grid. The GEP may include a field-programmable gate array (FPGA) configured to manage the acquired data and to execute at least one algorithm using the acquired data. The GEP may include a graphics processing unit (GPU) configured to execute at least one machine learning algorithm on at least one of the acquired data or data processed by the FPGA. The GPU may be configured to output data to a remote system via an input / output system.

The embodiments of the present disclosure provide a board and a server, which relates to the technical field of processor board card interconnection. By arranging the first internal connectors in the second internal connector configuration area and the second internal connectors in the first internal connector configuration area; the first processor is electrically connected to the first internal connectors through the first circuit, and the second processor is electrically connected to the second internal connectors through the second circuit, and the first circuit and the second circuit are arranged in an intersecting way. Based on the wiring design of the board of the embodiments of the present disclosure for multi-board interconnection, the complexity of the cable topology structure in the board group may be effectively simplified, thereby improving the maintenance efficiency of multi-card interconnection, and reducing the construction difficulty and maintenance cost.

The application discloses a multi-ring network data transmission architecture, a data processing node control method and a storage medium, relates to the field of ring network architecture control, and comprises the following steps: each data processing node is configured with a first independent communication board card, a second independent communication board card, a first processor board card, a backboard and a memory; the first independent communication board card and the second independent communication board card are connected in series to two ring networks; the first independent communication board card, the second independent communication board card, the first processor board card and the memory are all hot-pluggable; and the first independent communication board card, the second independent communication board card and the memory are in communication connection with the first processor board card. According to the application, the first independent communication board card is connected in series to the first ring network, and the second independent communication board card is connected in series to the second ring network, so that data processing can still be maintained by another independent communication board card and the ring network where the independent communication board card is located when any independent communication board card fails, and the operation reliability of the double-ring network data transmission architecture adopted by the DCS platform is improved.

The embodiment of the application discloses a data reading and writing device, method, processor, board and computer equipment, and relates to the technical field of semiconductors. The device comprises a first memory, a second memory, a first request processing unit connected with the first memory, and a second request processing unit connected with the second memory; the first request processing unit is used for determining a first target request from a first candidate request, and reading and writing first data indicated by the first target request from the first memory, the first candidate request is used for requesting reading and writing the first memory, and the first request processing unit comprises an input port for receiving the first candidate request sent by a second processor; the second request processing unit is used for determining a second target request from a second candidate request, and reading and writing second data indicated by the second target request from the second memory, the second candidate request is used for requesting reading and writing the second memory, and the second request processing unit comprises an input port for receiving the second candidate request sent by a first processor.

The embodiments of the present application provide a substrate and a method for preparing the same, a graphics processor board, and an electronic device, which relate to the field of semiconductor technology and are intended to improve the integrity and reliability of signal transmission. The substrate includes a trace arranged within the substrate, the trace including a first conductive structure and a second conductive structure, the second conductive structure being connected to the surface of the first conductive structure, and the second conductive structure covering at least a portion of the surface of the first conductive structure. Along a first direction from the first conductive structure to the second conductive structure, the second conductive structure includes alternating barrier layers and conductive layers, the resistivity of the conductive layer being less than the resistivity of the barrier layer. The above-mentioned substrate can be used for chip packaging to achieve interconnected signal transmission.

The present invention relates to a method for loading an application program in an embedded system, and belongs to the fields of communication technology and storage technology. When any main processor board in an embedded system fails, another normal main processor board is installed in the failed slot of a computer chassis. Without the need for manual parameter modification, the parameters in the main processor board in the slot can be dynamically modified and the application program in the board can be loaded automatically and quickly. The method for loading an application program in an embedded system proposed by the present invention perfectly solves the problem of "complex operation of replacing the main processor board and error-prone parameter configuration", realizes the rapid adaptive dynamic modification of the parameters of the main processor board in the computer chassis of the embedded system and the automatic loading of the application program, and improves the reliability of replacing the main processor board in the computer chassis.

The invention discloses a high-speed data network interaction and isolation controller and a data transmission method thereof. The controller comprises a processor board card, a coprocessor board card, a plurality of communication board cards and a backboard, the backboard adopts a high-speed connector design and is used for fixing the processor board card, the coprocessor board card and the communication board card and realizing power supply of the board cards and high-speed data interaction between the board cards; the processor board card performs data interaction with an upper computer by adopting a network communication protocol, and performs data interaction with the coprocessor board card by adopting a full-duplex high-speed serial communication protocol; the coprocessor board card performs data interaction with the communication board card through the backboard by adopting a redundant parallel full duplex high-speed serial protocol, and meanwhile, the coprocessor board card also supports data interaction with an upper computer by a user datagram protocol and a high-speed digital optical fiber transmission protocol; and the communication board card performs data interaction with the lower computer by adopting a high-speed digital optical fiber transmission protocol and a high-speed digital optical fiber interface.

The utility model relates to robot technical field, and disclose a kind of mainframe installation device for humanoid robot, including main body, the inside of main body is provided with mainframe installation mechanism, the mainframe installation mechanism includes equipment outer frame, the upper and lower ends of equipment outer frame are provided with threading slot, the both sides of threading slot are distributed with rubber pad strip, the inside top of equipment outer frame is provided with upper layer processor board card.This utility model provides protection to mainframe module part by the equipment outer frame carried in the inside of mainframe cavity, and the mainframe module part is composed of upper layer processor board card and lower power controller, respectively carried by slidable equipment box, and each group of equipment box two sides can be positioned by cooperating buckle, and the quick extraction and unlocking process of equipment box can be realized by cooperating button pressing, so that personnel do not need to remove element frequently in normal maintenance and maintenance operation, save removal step, facilitate maintenance and use.

The present invention discloses a system for loading FPGAs based on an LPC interface. The system is installed on a processor board with an LPC interface. The system configures the FPGA in SelectMAP mode. The system includes an FT2000 hardware system, BRAM, interface logic LPC_BRAM, and a Microblaze embedded system. The FT2000 hardware system obtains a V7 FPGA configuration data source file from the network and transmits it to the interface logic LPC_BRAM via LPC. The interface logic LPC_BRAM reads the data and writes it to the BRAM cache. The Microblaze embedded system reads the data from the BRAM cache and writes it to an external FLASH memory. Advantageously, the present invention constructs a complete embedded system with a cache, an LPC interface, a SelectMAP interface, and a Flash interface within a single chip, effectively saving board area, reducing hardware costs, and lowering the difficulty of board design, thereby achieving miniaturization, high integration, and high reliability of the embedded system.

The present invention generally relates to pulse capture electronics (PCE) of an imaging system that provides the ability to interface with, control, and test Read-Out Integrated Circuits (ROIC), and communicate the image data to a computing device for rendering and / or computational processing. The RIS-DC includes a single board signal processing architecture that is combined with a processor board to enable various operational requirements and varying ROICs to be configured to produce an operational imaging system.

A docking board removably coupled to a processor board that does not function when not operatively coupled to the docking board. The docking board sends power to and receive a control signal from the processor board when operatively coupled to the processor board and does not send power and does not receive a control signal when not operatively coupled to the processor board. The docking board is removably coupled to an expansion board that performs a computer function that is not performed by the processor board and the docking board. The docking board sends power and a control signal to the expansion board when the docking board is operatively coupled to the processor board and the expansion board, and does not send power and does not send a control signal to the expansion board when the docking board is not operatively coupled to the processor board and the expansion board.

The embodiment of the invention discloses a graphics processor starting method, a board card, a memory, a device, equipment and a medium. Wherein the graphics processor board card is provided with a standby interface used for connecting the graphics processor and the backup firmware memory, and a starting circuit used for switching firmware starting of the graphics processor; the graphics processor starting method comprises the steps that the interface state of the standby interface is detected, and starting firmware of the graphics processor is determined according to the interface state; and switching a starting circuit of the graphics processor according to the starting firmware, so that the graphics processor is started by adopting the starting firmware. According to the method, the startup firmware is determined to start the graphics processor according to the interface state of the standby interface, multiple startup modes can be provided for the graphics processor, and a backup firmware memory does not need to be welded to a graphics processor board card; the firmware repairing or upgrading efficiency and convenience of the graphics processor can be improved, and the repairing cost is reduced.

The invention discloses a data processing device, a processor, a board card and a data processing method. The data processing device may be included in a computing device of a combined processing device, which may also include an interface device and other processing devices. The data processing device interacts with other processing devices to jointly complete calculation operation specified by a user. The combined processing device can further comprise a storage device, and the storage device is connected with the computing device and the other processing devices and used for storing data of the computing device and the other processing devices. According to the scheme disclosed by the invention, a convolution operation scheme compatible with various particle size quantization formats is provided, the processing can be simplified, and the advantages of low bit width operation and small memory occupation of the particle size quantization formats are fully utilized.

A lawn vehicle network includes a charging station having a visual identifier, a lawn vehicle having a battery, a blade system, a drive system whose output effects lawn vehicle forward movement, a processor board connected to both systems, the processor board capable of processing image data and sending commands to both systems, and a vision assembly connected to the processor board and able to transmit image data to the processor board, and the processor board, having received the image data, able to, if the image data represent a first object, maintain the drive system's output at the time of that determination, if the image data represent a second object, change the drive system's output at the time of that determination, and if the image data represent the visual identifier, maintain the drive system's output or send a shutoff command to the vision assembly at the time of that determination.

The invention relates to a miniaturized low-power-consumption processor board, and belongs to the technical field of signal processing systems. The processor board takes Feiteng D2000 / 8 as a core, and can realize functions of display, control, storage, external data interface and the like; and the processor board comprises a Feiteng D2000 / 8 processor, a Feiteng bridge chip X100, a BMC (Baseboard Management Controller) and onboard DDR4 particles. The Feiteng CPU, the memory, the network, the serial port and other chips are integrated, more interfaces are reserved on the mainboard, the functions of display, control, storage, external data transmission and the like can be achieved, and the performance requirements in complex application scenes can be met.

The present application discloses a data processing apparatus, a processor, a board, and a data processing method. The data processing apparatus can be comprised in a computing apparatus of a combined processing apparatus, and the combined processing apparatus can further comprise an interface apparatus and another processing apparatus. The data processing apparatus interacts with the other processing apparatus to jointly complete a computing operation specified by a user. The combined processing apparatus can also comprise a storage apparatus. The storage apparatus is separately connected to the computing apparatus and the other processing apparatus, and is used for storing data of the computing apparatus and the other processing apparatus. The present application provides a convolution operation scheme compatible with various fine-grained quantization formats, which can simplify processing and make full use of the advantages of low bit width operation and small memory occupation of the fine-grained quantization formats.

An agriculture image analysis method includes acquiring crop canopy image data. Multiple agricultural features are extracted from edge processing of the image data and conducting data reduction to produce a real-time transmissible data set using an automated phenocam that uses a trained multiclass DCNN network. The real-time transmissible data is provided to a cloud based resource. An automated phenocam includes imaging and crop sensors, a local power source, and a single processor board that implements a trained multiclass DCNN network to produce a real-time transmissible data set regarding crop status.

A server system and a communication method of a server system are provided. The server system includes: at least one first processor board and a host server; the first processor board includes a first field programmable gate array chip and a first processor chip, the first field programmable gate array chip and the first processor chip being packaged and interconnected; the host server is configured to transmit host data to the first field programmable gate array chip through the switching network; and the first field programmable gate array chip is configured to process the host data, receive request data sent by the first processor chip, generate a communication protocol message according to processed host data and the request data, and transmit the communication protocol message to a target processor board through the switching network.

The present invention relates to a domestic KVM switching system, belonging to the field of computer system design. The present invention obtains DVI / HDMI input signals from two external main processor boards A and B, and performs KVM output switching and indication according to the current state by responding to external switching buttons or serial commands. The output interfaces include a DVI / HDMI output interface directly connected to the device, a USB power supply interface, two USB data differential interfaces, and two switching indicators that can directly indicate that the current output state is machine A or machine B, a DVI / HDMI debugging output interface related to debugging, and two debugging indicators. The software and hardware of this system can achieve a 100% domestic production rate.

The application provides a kind of multi-processor data interaction simulation system and method, the multi-processor data interaction simulation system includes: CPU simulation calculation unit includes multicore processor, data sharing memory and PCIe communication card, PCIe communication card includes first optical module interface and PCIe interface, multicore processor is connected with PCIe interface by one of high-speed PCIe bus or slot;FPGA processor board includes FPGA chip and second optical module interface;CPU simulation calculation unit is connected with at least one FPGA processor board by first optical module interface and second optical module interface;A plurality of CPU simulation calculation units are connected by first optical module interface;At least one CPU simulation calculation unit and at least one FPGA processor board carry out data interaction.The beneficial effects of the application are: without configuration file and data carrying time, improve the efficiency of data interaction.

The utility model discloses a marine optical fiber compass system data unit with four-compass input. The marine optical fiber compass system data unit comprises a CUP board, a communication interface board, an inter-board plug-in and fixing piece, a guide rail type supporting frame, a protection panel and a label. The CUP board comprises a main processor, a coprocessor, a CPU board power supply, a dual CAN bus interface, a Gyro4 half-duplex interface, a control unit power supply and communication interface and an external clock system; the communication interface board comprises a Gyro1-3 interface, a BAM interface, a satellite guide receiving and relay / output interface, a dry contact signal interface, four groups of output interfaces, two paths of RS485 multifunctional interfaces, a communication power supply module, a system power supply, a redundant power supply detection module and a filtering and protection circuit. The inter-board plug-in and fixing piece comprises a pin header, a female header, a hexagonal copper column for fixing, a flat gasket, an elastic gasket, a nut and a screw. According to the utility model, four paths of compass signals can be accessed, so that information such as multi-compass redundant course angles, course angular speeds and the like can be provided for ships.

The invention discloses an unmanned aerial vehicle accurate landing identification module which comprises a support, a laser ranging module and a visual processor board card are fixedly installed on one side of the support, and a camera is fixedly installed on one side of the visual processor board card; a fisheye lens is fixedly mounted on the camera; an infrared band-pass optical filter is fixedly mounted on one side, close to the fisheye lens, of the camera; the side, away from the laser ranging module, of the support is evenly and fixedly connected with connecting blocks. A threaded groove is formed in the connecting block; the laser ranging module is used for measuring the actual distance between the unmanned aerial vehicle and the beacon light panel; according to the accurate landing identification module for the unmanned aerial vehicle, the laser ranging module, the visual processor board card and the camera are arranged on the support, so that accurate landing of the unmanned aerial vehicle can work at night and is not affected by illumination intensity, and therefore the working efficiency of the unmanned aerial vehicle during task execution at night is improved, and the working efficiency of the unmanned aerial vehicle is improved. And the applicability and the flexibility of the unmanned aerial vehicle precise landing identification module are improved.

The utility model discloses a quantum random number generator and a quantum communication device, and relates to the quantum communication technology field, the quantum random number generator comprises a cabinet, a power supply, a light source, a photoelectric detector, a processor, a PCBA board, a first heat radiation assembly, a second heat radiation assembly, a third heat radiation assembly and a tail fiber storage box; the light source, the photoelectric detector and the processor are fixedly arranged on the PCBA board, the PCBA board is fixedly arranged on the inner side of the bottom of the case, the first heat dissipation assembly is fixedly arranged on the inner side of one side wall of the case, the second heat dissipation assembly is fixedly and tightly arranged on the light source, and the third heat dissipation assembly is fixedly and tightly arranged on the processor. The tail fiber storage box is fixedly arranged on the inner side of the bottom of the machine case, the machine case, the light source, the photoelectric detector, the processor, the PCBA board, the first heat dissipation assembly, the second heat dissipation assembly, the third heat dissipation assembly and the tail fiber storage box are all arranged in the machine case, and the stability of the quantum random number generator is improved.

The embodiment of the invention provides a substrate and a preparation method thereof, a graphics processor board card and electronic equipment, relates to the technical field of semiconductors, and aims to improve the integrity and reliability of signal transmission. The substrate comprises a wire arranged in the substrate, the wire comprises a first conductive structure and a second conductive structure, the second conductive structure is connected with the surface of the first conductive structure, and the second conductive structure covers at least part of the surface of the first conductive structure. In the first direction from the first conductive structure to the second conductive structure, the second conductive structure comprises barrier layers and conductive layers which are alternately arranged, and the resistivity of the conductive layers is smaller than that of the barrier layers. The substrate can be used for packaging a chip so as to realize interconnection transmission of signals.

A mainboard includes a plurality of interfaces, a first interface of the plurality of interfaces is configured to be connected to the processor board card having a processor circuit, a second interface of the plurality of interfaces is configured to be connected to a non-processor board card, and the first interface and the second interface are connected to each other via a communication circuit; for the mainboard, a connection-centric design idea is adopted, the processor board card is regarded to have the same status as the non-processor board card; because no processor circuit is provided, and only the first interface connected to the processor board card needs to be provided, compared with an original mainboard, an area of the board card in the present application is reduced, and the processor board card and other non-processor board cards may be connected to the mainboard in a stacked manner.

A cold-plate forming a circulating liquid cooled heat sink has a body 130 forming an inner volume having inlet and outlet chambers in fluid communication (see fig 4) with inlets and outlets of a jet impingement plate assembly 155, 530 (fig 5b). The body is enclosed by an outer cover plate 135. The cold-plate can be fixed to one side of a processor board 101 (such a PCB card with a GPU 104) and to a backing plate 110 on the opposite side of the board, so the board is sandwiched. The jet impingement plate is arranged over the hottest component, the processor. The other components are cooled by the rest of the cold-plate & backing plate assembly. Multiple cards, each with the heatsink assembly, maybe mounted side by side (figures 7,8)

The invention discloses a data processing device, a processor, a board card and a data processing method. The data processing device may be included in a computing device of a combined processing device, which may also include an interface device and other processing devices. The data processing device interacts with other processing devices to jointly complete calculation operation specified by a user. The combined processing device can further comprise a storage device, and the storage device is connected with the computing device and the other processing devices and used for storing data of the computing device and the other processing devices. According to the scheme disclosed by the invention, a vector operation scheme fusing various particle size quantizations is provided, the processing can be simplified, and the advantages of low bit width operation and small memory occupation of a particle size quantization format are fully utilized.