189 results about "Processor board" patented technology

A redundant file server includes at least two dual processor boards. Each physical processor has two logical processors. The first logical processor of the first physical processor of each board executes storage system code under the Microsoft NT™ operating system. The second logical processor of the first physical processor of each board executes control station code under the Linux operating system. The first logical processor of the second physical processor of each board executes data mover code. The second logical processor of the second physical processor of each board is kept in a stand-by mode for assuming data mover functions upon failure of the first logical processor of the second physical processor on the first or second board.

A Pseudo-Ethernet switch has a routing table that uses Ethernet media-access controller (MAC) addresses to route Ethernet packets through a switch fabric between an input port and an output port. However, the input port and output port have Peripheral Component Interconnect Express (PCIE) interfaces that read and write PCI-Express packets to and from host-processor memories. When used in a blade system, host processor boards have PCIE physical links that connect to the PCIE ports on the Pseudo-Ethernet switch. The Pseudo-Ethernet switch does not have Ethernet MAC and Ethernet physical layers, saving considerable hardware. The switch fabric can be a cross-bar switch or can be a shared memory that stores Ethernet packet data embedded in the PCIE packets. Write and read pointers for a buffer storing an Ethernet packet in the shared memory can be passed from input to output port to perform packet switching.

A replacement device for a conventional bill acceptor in a gaming machine, located in the same space as the bill acceptor, has a bill acceptor or voucher reader / printer, plus at least a fingerprint reader. In one preferred embodiment, the new device has a bill acceptor, fingerprint reader, magnetic strip card reader, and an LCD screen. All interface to the existing game processor board using the bill acceptor's existing serial connection, and optionally to backend systems using an ethernet connection directly from the new device.

The present invention relates to a configurable emissive display tile, e.g. an organic light-emitting diode (OLED) display tile and associated methods for use in a tiled large-screen display application. The OLED tile assembly of the present invention is capable of operating either as an autonomous display or, alternatively, may operate within a set of OLED display tiles forming a larger tiled display. An embodiment of an OLED tile assembly (100) according to an embodiment of the present invention is shown in FIG. 1C, including a power supply (158), a cooling system with cooling fans (160) and cooling blocks (146) and a control system, comprising a control board (154) with processor, an OLED board (142) and a substrate (140). It furthermore includes a digital video interface and an automatic addressing system The present invention further includes a method of initial assembly, automatic configuration, and calibration of the tiled OLED display and a method of replacing, adding, or removing one or more OLED tile assemblies in a larger tiled display.

A portable coordinate measurement machine having three articulating arm transfer members can provide accurate measurements. The transfer members can be single tube assemblies. The transfer members can each be rotatably joined by relatively short articulating joint assemblies allowing relative rotation of adjacent transfer members about two degrees of freedom. Encoders can be used to measure the relative rotation about each of the degrees of freedom, and signals from the encoders can be digitized by processor boards positioned within the transfer members. Processor boards can be placed in tandem in the transfer members, and one or more of the processor boards can be mounted on a rotatable assembly. Slip rings can electrically couple all of the processor boards to allow for infinite rotatability of the articulating arm.

A method, system, and medium for dynamic load balancing of a multi-domain server are provided. A first computer system includes a plurality of domains and a plurality of system processor boards. A management console is coupled to the first computer system and is configurable to monitor the plurality of domains. An agent is configurable to gather a first set of information relating to the domains. The agent includes one or more computer programs that are configured to be executed on the first computer system. The agent is configurable to automatically migrate one or more of the plurality of system processor boards among the plurality of domains in response to the first set of gathered information relating to the domains.

A redundant file server includes at least two dual processor boards. Each physical processor has two logical processors. The first logical processor of the first physical processor of each board executes storage system code under the Microsoft NT(TM) operating system. The second logical processor of the first physical processor of each board executes control station code under the Linux operating system. The first logical processor of the second physical processor of each board executes data mover code. The second logical processor of the second physical processor of each board is kept in a stand-by mode for assuming data mover functions upon failure of the first logical processor of the second physical processor on the first or second board.

A portable coordinate measurement machine having three articulating arm transfer members can provide accurate measurements. The transfer members can be single tube assemblies. The transfer members can each be rotatably joined by relatively short articulating joint assemblies allowing relative rotation of adjacent transfer members about two degrees of freedom. Encoders can be used to measure the relative rotation about each of the degrees of freedom, and signals from the encoders can be digitized by processor boards positioned within the transfer members. Processor boards can be placed in tandem in the transfer members, and one or more of the processor boards can be mounted on a rotatable assembly. Slip rings can electrically couple all of the processor boards to allow for infinite rotatability of the articulating arm.

A chassis partition architecture of a chassis for configuring a multi-processor system is provided to fulfill flexibility, serviceability and configurability of a multi-processor system. The partition architecture mainly includes the partition architecture mainly includes a node partition, a expansion partition and a function partition. The node partition is located at a middle section of the chassis, mainly for containing several processor boards that are configured vertically and lengthwise. The expansion partition is located behind the node partition, mainly for containing several expansion boards that are configured vertically and lengthwise. And the function partition is located at a front section of the chassis lower than the node partition and the expansion partition, mainly for containing a plurality of function cards that are configured upside-down vertically and lengthwise.

Provided is a storage unit for depositing articles for subsequent retrieval. The storage unit includes a plurality of storage compartments with at least one retractable and foldable shelf member within each storage compartment. The storage unit also includes a set of doors configured to cooperate with each other and movable between a closed configuration which disallows access to the plurality of storage compartments and an opened configuration which allows access to the plurality of storage compartments. A control system which includes a computer, a processor board and software is also included with the storage unit. The control system may receive and process an input allowing the set of doors to be moved to an open configuration and may selectively define an access opening between the set of doors for accessing a storage section selected from at least one of the storage compartments.

A personal computing device comprising: a processor, an onboard memory, an accelerometer, a gyroscope, and a display; a computer program to create an exercise analysis application comprising: a software module configured to receive data from the accelerometer and the gyroscope that are associated with the bodily motion of a user in three dimensions; a software module configured to place the device in a learning mode, the learning mode comprising recording the data of the user performing a defined exercise to generate a statistical model for the exercise; a software module configured to place the device in a normal mode, the normal mode comprising applying a probabilistic analysis to the bodily motion data to identify an exercise event, classify the exercise by comparison to a recorded model; and a software module configured to apply an analysis to the bodily motion data to score the user's exercise form.

Virtual machine environments are provided in the switches that form a network, with the virtual machines executing network services previously performed by dedicated appliances. The virtual machines can be executed on a single multi-core processor in combination with normal switch functions or on dedicated services processor boards. Packet processors analyze incoming packets and add a services tag containing services entries to any packets. Each switch reviews the services tag and performs any network services resident on that switch. This allows services to be deployed at the optimal locations in the network. The network services may be deployed by use of drag and drop operations. A topology view is presented, along with network services that may be deployed. Services may be selected and dragged to a single switch or multiple switches. The management tool deploys the network services software, with virtual machines being instantiated on the switches as needed.

A video surveillance camera comprising an image sensor, first housing, second housing, electronic circuit, and thermal barrier. The image sensor is located in the first housing, and the electronic circuit is located in the second housing. The thermal barrier has first and second sides with the first side located adjacent to the first housing and the second side located adjacent to the second housing. The image sensor and other electronics, such as the processor board associated with the image sensor or the camera power supply, are located in separate housings or chambers that are separated and insulated from each other by a thermal barrier, thereby minimizing the heat generated by the processor electronics or power supply from being transferred to the area of the image sensor.

The present invention is a method and apparatus enabling a low cost hardware upgrade path and low cost processor board retrofit for gaming machines. The enabling features include a two-board set made up of an industry standard form factor processor board (a single board system, able to support an operating system) coupled to an I / O adapter board, and further having a specially architected game kernel based on a UNIX-compatible operating system. The game kernel provides a consistent API to game applications, enabling quick and easy use of new hardware features while providing backward compatibility for existing game applications.

A system and method for managing performance states of a processor. An enclosure comprises a first processing board with a processor and a second processing board with a processor. A service processor may also be coupled to the enclosure via an interconnect. The second processing board is configured to store a value indicative of a maximum processor performance state for a processor on the second board. In response to a detected request for a transition to a first processor performance state, the processor on the second board is configured to transition to the first processor performance state, if the first processor state is less than or equal to the maximum processor performance state; and transition to the maximum processor performance state, if the first processor state is greater than the maximum processor state. The second processor board may store the value in response to a an operating environment condition detected elsewhere within the enclosure.

A computer management system attains, through one line, the uniform and steady system management through an agent such as monitoring of fault and power control in a computer connected by LAN as well as a public line, and system management for an off-state of the computer or abnormal operation state of the computer such as remote power control and notice and diagnosis of critical fault by the direct connection with a service processor through the line. The system includes an agent connected to a computer to be managed for executing instructions on the computer to be managed, a service processor board having a processor independent from the computer to be managed for monitoring fault in the computer to be managed and controlling power of the computer to be managed, a manager for executing instructions on a management computer and conducting controls such as fault monitoring and power control through the agent over a network including a public line, and a service processor manager directly connected to the service processor for conducting remote power-on and receiving and diagnosing critical fault. The service processor and the service processor manager are provided with switching circuits for switching an asynchronous interface for remotely connecting to the computer to be managed and an asynchronous interface for directly connecting to a local processor of the service processor.

An information handling system is provided which includes a dynamic interrupt router for balancing interrupt assignments among a plurality of devices requesting interrupt assignments. The system balances interrupt assignments among both fixed devices mounted on the processor board and interrupt assignments to devices situated in expansion slots. When the system is populated with a large number of devices relative to the number of available interrupts, improved interrupt sharing is desirably achieved by causing a device which generates a large number of interrupt requests to share a common interrupt with a device which generates a lower number of interrupts.

The invention relates to an automated terminal monitoring device for a distribution network. The automated terminal monitoring device is used for monitoring power distribution equipment and comprises a processor board card, an instrument transformer sampling board card and an input / output control board, wherein an instrument transformer detection input circuit is arranged on the instrument transformer sampling board card, and a processor module and an alternating current sampling circuit which are mutually connected are arranged on the processor board card; a switching value input / output conversion circuit is arranged on the input / output control board card. A hardware structure is divided in a board card way, and the board cards are communicated by a bus communication protocol, so that the integrated design of the traditional hardware is avoided, and the working efficiency and the maintainability of a system can be effectively improved. The invention also relates to a monitoring system based on the automated terminal monitoring device for the distribution network. Through a combined architecture mode, the networking monitoring mode is realized for a plurality of pieces of power distribution equipment, the interaction and communication between data of monitored power distribution equipment are realized, and the monitoring system can be suitable for various different monitoring requirements.

Virtual machine environments are provided in the switches that form a network, with the virtual machines executing network services previously performed by dedicated appliances. The virtual machines can be executed on a single multi-core processor in combination with normal switch functions or on dedicated services processor boards. Packet processors analyze incoming packets and add a services tag containing services entries to any packets. Each switch reviews the services tag and performs any network services resident on that switch. This allows services to be deployed at the optimal locations in the network. The network services may be deployed by use of drag and drop operations. A topology view is presented, along with network services that may be deployed. Services may be selected and dragged to a single switch or multiple switches. The management tool deploys the network services software, with virtual machines being instantiated on the switches as needed.

A physical hardware architecture is provided to fulfill flexibility, serviceability and configurability of a multi-processor system. The architecture mainly includes a bottom plane, plural processor boards and a function board. On the front section of the top side of the bottom plane, the processor boards are configured thereon. The function board faces downwards and is configured in an edge-to-edge connection with the front edge of the bottom plane. Function card(s) may be configured vertically on the bottom surface of the function board. On the rear section of the top side of the bottom plane expansion card(s) are configured vertically. With main system fan(s) located on the top of the function board and auxiliary system fan configured under the bottom plane, the multi-processor system will also achieve optimum cooling capability through the architecture.

The invention relates to a controller applied to a multiphase motor speed adjusting system. The controller comprises a bus board, a power source board card, a main processor board card, an analog quantity conditioning board card, a switch quantity input and output board card, an optical fiber driving board card and a communication through-connection board card, wherein the power source board card provides various power sources to all the other board cards through the bus board, driving and feedback signals of the optical fiber driving board card, a switch quantity signal of the switch quantity input and output board card, an analog quantity signal of the analogy quantity conditioning board card, a communication signal of the communication through-connection board card perform information interaction with the main processor board card through the bus board, and the communication through-connection board card and the main processor board card respectively at least have communication with an upper computer. The controller has the advantages of being high in modularization degree, having flexible expandability, being capable of not only controlling the complex multiphase motor speed adjusting system in real time, but also greatly enhancing the expanding flexibility due to the fact the bus board is deigned in a bus mode, and being capable of effectively controlling development cost, shortening the development period and meanwhile improving equipment reliability.

Virtual machine environments are provided in the switches that form a network, with the virtual machines executing network services previously performed by dedicated appliances. The virtual machines can be executed on a single multi-core processor in combination with normal switch functions or on dedicated services processor boards. Packet processors analyze incoming packets and add a services tag containing services entries to any packets. Each switch reviews the services tag and performs any network services resident on that switch. This allows services to be deployed at the optimal locations in the network. The network services may be deployed by use of drag and drop operations. A topology view is presented, along with network services that may be deployed. Services may be selected and dragged to a single switch or multiple switches. The management tool deploys the network services software, with virtual machines being instantiated on the switches as needed.

A physical hardware architecture is provided to fulfill flexibility, serviceability and configurability of a multi-processor system. The architecture mainly includes a bottom plane, plural processor boards and a function board. On the front section of the top side of the bottom plane, the processor boards are configured thereon. The function board faces downwards and is configured in an edge-to-edge connection with the front edge of the bottom plane. Function card(s) may be configured vertically on the bottom surface of the function board. On the rear section of the top side of the bottom plane expansion card(s) are configured vertically. With main system fan(s) located on the top of the function board and auxiliary system fan configured under the bottom plane, the multi-processor system will also achieve optimum cooling capability through the architecture.

The present invention relates to a link aggregation apparatus and method for aggregating multiple physical interface ports into a single logical link and using the aggregated logical links. The link aggregation means aggregates a plurality of physical interface ports into a logical link and utilizes the logical link in the main processing board connected to a plurality of line cards each having a plurality of physical interface ports. The link aggregation device includes a system management unit, a mapping table, an IPC message control unit, and at least one application. A system management unit is provided with a plurality of virtual interfaces to which ports of the physical interface are to be allocated, and manages the interfaces while managing setting information and failure information of the virtual interfaces. A mapping table is used to assign at least two of the plurality of physical interface ports to at least one of the plurality of virtual interfaces. An IPC message control unit sends IPC messages between the line card and the main processor board using a mapping table. The application performs a specified unique function in response to IPC messages sent to the virtual interface.

Techniques for implementing assess to Android applications and native Window application on Android devices and systems. A processor board includes a processor that is configured to run a full version of a Windows operating system and Windows applications. The processor board is configured to be communicatively coupled to the processor board in an Android device, such as a Smartphone or tablet. Upon operations and when the processor board is communicatively coupled to the Android device, a user of the Android device is enabled to selectively run Android applications and Windows applications, with the Windows applications being executed natively on the processor board. The processor board may be implemented in a computing card that is approximately the size of a credit card or smaller, which in turn may be coupled to the Android device via a backpack or similar means. The processor board may also be disposed within the same housing as the Android device.

Redundant systems are often provided with identically mounted processor boards which function according to a lockstep operation. The basic condition for the implementation of a lockstep system is the deterministic behaviour of all of the constituents contained in the board, such as CPUs, chip sets, main memory etc. According to the invention, deterministic behaviour signifies that said constituents supply identical results at identical times, in an error-free case, when the constituents receive identical stimuli at identical times. Deterministic behaviour also presupposes the use of interfaces in clock-controlled synchronism. Asynchronous interfaces cause a certain temporal indeterminacy in the system in many cases, whereby the entire synchronised behaviour of the system cannot be maintained. In order to thus be able to carry out a lockstep operation, the invention relates to a method for the synchronisation of external events which are supplied to a processor (CPU) and influence the same. The external events are intermediately stored accordingly and the processors are presented at identical points in the execution of commands. Problems which are created by the capacity of modern processors to execute commands in parallel are avoided by the fact that the parallel execution of the processors is stopped before the desired point in the command execution is reached and said point is then reached exactly in the single step mode.

A computer adapted for force-air cooling of a processor. The computer includes a board supporting the processor and a heat sink mounted such with its base plate contacting the processor. A primary mount supports the heat sink near the processor, and a portion of the heat sink base plate extends outward a distance or overhang length from the primary mount to an edge. The apparatus includes a secondary heat sink mounting assembly supported upon the processor board that includes a damping element with an resilient body positioned proximate to the edge of the base plate, whereby the body abuts the base plate during movement of the base plate toward the board, e.g., upon application of a dynamic or shock load that causes the overhanging portions of the base plate of the heat sink to vibrate or oscillate about the support locations of the primary mount.

A data processing system suitable for use in a scalable system, including a first set of processors, a first system memory, and scalability logic to connect the data processing system to a second data processing system to form a scaled system. A set of scalability ports are connected to the scalability logic to receive scalability cables connecting the first system to the second system or to another processor board within the same chassis. The system includes system management to cause each of the system's scalability ports to issue an identifiable signal. System management also detects the reception of an identifiable signal, sent by another system, received by any of the scalability ports and reports the reception of the signal to a system management of the second system to determine which ports of the two systems are connected by the cable.

Virtual machine environments are provided in the switches that form a network, with the virtual machines executing network services previously performed by dedicated appliances. The virtual machines can be executed on a single multi-core processor in combination with normal switch functions or on dedicated services processor boards. Packet processors analyze incoming packets and add a services tag containing services entries to any packets. Each switch reviews the services tag and performs any network services resident on that switch. This allows services to be deployed at the optimal locations in the network. The network services may be deployed by use of drag and drop operations. A topology view is presented, along with network services that may be deployed. Services may be selected and dragged to a single switch or multiple switches. The management tool deploys the network services software, with virtual machines being instantiated on the switches as needed.