28 results about "Processor board" patented technology

A data processing apparatus, a processor, a board card, and a data processing method. The data processing apparatus may be comprised by a combined processing apparatus (20), the combined processing apparatus (20) comprising a computing apparatus (201), an interface apparatus (202), a processing apparatus (203) and a storage apparatus (204). The computing apparatus (201) is configured to execute an operation specified by a user, so as to execute deep learning or machine learning calculation. The computing apparatus (201) may interact with the processing apparatus (203) by means of the interface apparatus (202), so as to jointly complete the operation specified by the user. The interface apparatus (202) is used to transmit data and a control instruction between the computing apparatus (201) and the processing apparatus (203). The storage apparatus (204) is used to store data of the computing apparatus (201) and the processing apparatus (203). The data processing apparatus provides a vector computation scheme integrating different types of fine-grained quantization, so that processing can be simplified, and the advantages of a low bit width operation and small memory occupation of a fine-grained quantization format are fully utilized.

A Grid Edge Platform or a processor board may be configured to monitor a utility grid and quickly determine or respond to a fault condition of the utility grid. The GEP may include a data acquisition system configured to acquire data from one or more sensors of the utility grid. The GEP may include a field-programmable gate array (FPGA) configured to manage the acquired data and to execute at least one algorithm using the acquired data. The GEP may include a graphics processing unit (GPU) configured to execute at least one machine learning algorithm on at least one of the acquired data or data processed by the FPGA. The GPU may be configured to output data to a remote system via an input / output system.

The embodiments of the present disclosure provide a board and a server, which relates to the technical field of processor board card interconnection. By arranging the first internal connectors in the second internal connector configuration area and the second internal connectors in the first internal connector configuration area; the first processor is electrically connected to the first internal connectors through the first circuit, and the second processor is electrically connected to the second internal connectors through the second circuit, and the first circuit and the second circuit are arranged in an intersecting way. Based on the wiring design of the board of the embodiments of the present disclosure for multi-board interconnection, the complexity of the cable topology structure in the board group may be effectively simplified, thereby improving the maintenance efficiency of multi-card interconnection, and reducing the construction difficulty and maintenance cost.

The application discloses a multi-ring network data transmission architecture, a data processing node control method and a storage medium, relates to the field of ring network architecture control, and comprises the following steps: each data processing node is configured with a first independent communication board card, a second independent communication board card, a first processor board card, a backboard and a memory; the first independent communication board card and the second independent communication board card are connected in series to two ring networks; the first independent communication board card, the second independent communication board card, the first processor board card and the memory are all hot-pluggable; and the first independent communication board card, the second independent communication board card and the memory are in communication connection with the first processor board card. According to the application, the first independent communication board card is connected in series to the first ring network, and the second independent communication board card is connected in series to the second ring network, so that data processing can still be maintained by another independent communication board card and the ring network where the independent communication board card is located when any independent communication board card fails, and the operation reliability of the double-ring network data transmission architecture adopted by the DCS platform is improved.

The embodiment of the application discloses a data reading and writing device, method, processor, board and computer equipment, and relates to the technical field of semiconductors. The device comprises a first memory, a second memory, a first request processing unit connected with the first memory, and a second request processing unit connected with the second memory; the first request processing unit is used for determining a first target request from a first candidate request, and reading and writing first data indicated by the first target request from the first memory, the first candidate request is used for requesting reading and writing the first memory, and the first request processing unit comprises an input port for receiving the first candidate request sent by a second processor; the second request processing unit is used for determining a second target request from a second candidate request, and reading and writing second data indicated by the second target request from the second memory, the second candidate request is used for requesting reading and writing the second memory, and the second request processing unit comprises an input port for receiving the second candidate request sent by a first processor.

The utility model relates to robot technical field, and disclose a kind of mainframe installation device for humanoid robot, including main body, the inside of main body is provided with mainframe installation mechanism, the mainframe installation mechanism includes equipment outer frame, the upper and lower ends of equipment outer frame are provided with threading slot, the both sides of threading slot are distributed with rubber pad strip, the inside top of equipment outer frame is provided with upper layer processor board card.This utility model provides protection to mainframe module part by the equipment outer frame carried in the inside of mainframe cavity, and the mainframe module part is composed of upper layer processor board card and lower power controller, respectively carried by slidable equipment box, and each group of equipment box two sides can be positioned by cooperating buckle, and the quick extraction and unlocking process of equipment box can be realized by cooperating button pressing, so that personnel do not need to remove element frequently in normal maintenance and maintenance operation, save removal step, facilitate maintenance and use.

The present invention generally relates to pulse capture electronics (PCE) of an imaging system that provides the ability to interface with, control, and test Read-Out Integrated Circuits (ROIC), and communicate the image data to a computing device for rendering and / or computational processing. The RIS-DC includes a single board signal processing architecture that is combined with a processor board to enable various operational requirements and varying ROICs to be configured to produce an operational imaging system.

A docking board removably coupled to a processor board that does not function when not operatively coupled to the docking board. The docking board sends power to and receive a control signal from the processor board when operatively coupled to the processor board and does not send power and does not receive a control signal when not operatively coupled to the processor board. The docking board is removably coupled to an expansion board that performs a computer function that is not performed by the processor board and the docking board. The docking board sends power and a control signal to the expansion board when the docking board is operatively coupled to the processor board and the expansion board, and does not send power and does not send a control signal to the expansion board when the docking board is not operatively coupled to the processor board and the expansion board.

The embodiment of the invention discloses a graphics processor starting method, a board card, a memory, a device, equipment and a medium. Wherein the graphics processor board card is provided with a standby interface used for connecting the graphics processor and the backup firmware memory, and a starting circuit used for switching firmware starting of the graphics processor; the graphics processor starting method comprises the steps that the interface state of the standby interface is detected, and starting firmware of the graphics processor is determined according to the interface state; and switching a starting circuit of the graphics processor according to the starting firmware, so that the graphics processor is started by adopting the starting firmware. According to the method, the startup firmware is determined to start the graphics processor according to the interface state of the standby interface, multiple startup modes can be provided for the graphics processor, and a backup firmware memory does not need to be welded to a graphics processor board card; the firmware repairing or upgrading efficiency and convenience of the graphics processor can be improved, and the repairing cost is reduced.

The invention discloses a data processing device, a processor, a board card and a data processing method. The data processing device may be included in a computing device of a combined processing device, which may also include an interface device and other processing devices. The data processing device interacts with other processing devices to jointly complete calculation operation specified by a user. The combined processing device can further comprise a storage device, and the storage device is connected with the computing device and the other processing devices and used for storing data of the computing device and the other processing devices. According to the scheme disclosed by the invention, a convolution operation scheme compatible with various particle size quantization formats is provided, the processing can be simplified, and the advantages of low bit width operation and small memory occupation of the particle size quantization formats are fully utilized.

The invention relates to a miniaturized low-power-consumption processor board, and belongs to the technical field of signal processing systems. The processor board takes Feiteng D2000 / 8 as a core, and can realize functions of display, control, storage, external data interface and the like; and the processor board comprises a Feiteng D2000 / 8 processor, a Feiteng bridge chip X100, a BMC (Baseboard Management Controller) and onboard DDR4 particles. The Feiteng CPU, the memory, the network, the serial port and other chips are integrated, more interfaces are reserved on the mainboard, the functions of display, control, storage, external data transmission and the like can be achieved, and the performance requirements in complex application scenes can be met.

The present application discloses a data processing apparatus, a processor, a board, and a data processing method. The data processing apparatus can be comprised in a computing apparatus of a combined processing apparatus, and the combined processing apparatus can further comprise an interface apparatus and another processing apparatus. The data processing apparatus interacts with the other processing apparatus to jointly complete a computing operation specified by a user. The combined processing apparatus can also comprise a storage apparatus. The storage apparatus is separately connected to the computing apparatus and the other processing apparatus, and is used for storing data of the computing apparatus and the other processing apparatus. The present application provides a convolution operation scheme compatible with various fine-grained quantization formats, which can simplify processing and make full use of the advantages of low bit width operation and small memory occupation of the fine-grained quantization formats.

An agriculture image analysis method includes acquiring crop canopy image data. Multiple agricultural features are extracted from edge processing of the image data and conducting data reduction to produce a real-time transmissible data set using an automated phenocam that uses a trained multiclass DCNN network. The real-time transmissible data is provided to a cloud based resource. An automated phenocam includes imaging and crop sensors, a local power source, and a single processor board that implements a trained multiclass DCNN network to produce a real-time transmissible data set regarding crop status.

A server system and a communication method of a server system are provided. The server system includes: at least one first processor board and a host server; the first processor board includes a first field programmable gate array chip and a first processor chip, the first field programmable gate array chip and the first processor chip being packaged and interconnected; the host server is configured to transmit host data to the first field programmable gate array chip through the switching network; and the first field programmable gate array chip is configured to process the host data, receive request data sent by the first processor chip, generate a communication protocol message according to processed host data and the request data, and transmit the communication protocol message to a target processor board through the switching network.

The application provides a kind of multi-processor data interaction simulation system and method, the multi-processor data interaction simulation system includes: CPU simulation calculation unit includes multicore processor, data sharing memory and PCIe communication card, PCIe communication card includes first optical module interface and PCIe interface, multicore processor is connected with PCIe interface by one of high-speed PCIe bus or slot;FPGA processor board includes FPGA chip and second optical module interface;CPU simulation calculation unit is connected with at least one FPGA processor board by first optical module interface and second optical module interface;A plurality of CPU simulation calculation units are connected by first optical module interface;At least one CPU simulation calculation unit and at least one FPGA processor board carry out data interaction.The beneficial effects of the application are: without configuration file and data carrying time, improve the efficiency of data interaction.

The utility model discloses a marine optical fiber compass system data unit with four-compass input. The marine optical fiber compass system data unit comprises a CUP board, a communication interface board, an inter-board plug-in and fixing piece, a guide rail type supporting frame, a protection panel and a label. The CUP board comprises a main processor, a coprocessor, a CPU board power supply, a dual CAN bus interface, a Gyro4 half-duplex interface, a control unit power supply and communication interface and an external clock system; the communication interface board comprises a Gyro1-3 interface, a BAM interface, a satellite guide receiving and relay / output interface, a dry contact signal interface, four groups of output interfaces, two paths of RS485 multifunctional interfaces, a communication power supply module, a system power supply, a redundant power supply detection module and a filtering and protection circuit. The inter-board plug-in and fixing piece comprises a pin header, a female header, a hexagonal copper column for fixing, a flat gasket, an elastic gasket, a nut and a screw. According to the utility model, four paths of compass signals can be accessed, so that information such as multi-compass redundant course angles, course angular speeds and the like can be provided for ships.

A mainboard includes a plurality of interfaces, a first interface of the plurality of interfaces is configured to be connected to the processor board card having a processor circuit, a second interface of the plurality of interfaces is configured to be connected to a non-processor board card, and the first interface and the second interface are connected to each other via a communication circuit; for the mainboard, a connection-centric design idea is adopted, the processor board card is regarded to have the same status as the non-processor board card; because no processor circuit is provided, and only the first interface connected to the processor board card needs to be provided, compared with an original mainboard, an area of the board card in the present application is reduced, and the processor board card and other non-processor board cards may be connected to the mainboard in a stacked manner.

A cold-plate forming a circulating liquid cooled heat sink has a body 130 forming an inner volume having inlet and outlet chambers in fluid communication (see fig 4) with inlets and outlets of a jet impingement plate assembly 155, 530 (fig 5b). The body is enclosed by an outer cover plate 135. The cold-plate can be fixed to one side of a processor board 101 (such a PCB card with a GPU 104) and to a backing plate 110 on the opposite side of the board, so the board is sandwiched. The jet impingement plate is arranged over the hottest component, the processor. The other components are cooled by the rest of the cold-plate & backing plate assembly. Multiple cards, each with the heatsink assembly, maybe mounted side by side (figures 7,8)

The invention discloses a data processing device, a processor, a board card and a data processing method. The data processing device may be included in a computing device of a combined processing device, which may also include an interface device and other processing devices. The data processing device interacts with other processing devices to jointly complete calculation operation specified by a user. The combined processing device can further comprise a storage device, and the storage device is connected with the computing device and the other processing devices and used for storing data of the computing device and the other processing devices. According to the scheme disclosed by the invention, a vector operation scheme fusing various particle size quantizations is provided, the processing can be simplified, and the advantages of low bit width operation and small memory occupation of a particle size quantization format are fully utilized.

A Grid Edge Platform or a processor board may be configured to monitor a utility grid and quickly determine or respond to a fault condition of the utility grid. The GEP may include a data acquisition system configured to acquire data from one or more sensors of the utility grid. The GEP may include a field-programmable gate array (FPGA) configured to manage the acquired data and to execute at least one algorithm using the acquired data. The GEP may include a graphics processing unit (GPU) configured to execute at least one machine learning algorithm on at least one of the acquired data or data processed by the FPGA. The GPU may be configured to output data to a remote system via an input / output system.

A cooling system that comprises a liquid cooled heat sink is described. The liquid cooled heat sink comprises a body defining an inner volume comprising an inlet chamber and an outlet chamber, the inlet chamber being in fluid communication with the outlet chamber though at least one jet impingement plate, such that operatively liquid enters the liquid cooled heat sink into the inlet chamber and passes through the at last one jet impingement plate prior to exiting the liquid cooled heat sink from the outlet chamber. The system is configured to effectively sandwich a processor board between the liquid cooled heat sink and a backing plate so as to effectively thermally conduct heat generated by components of the processor board through the body of the liquid cooled heat sink into a fluid that is passing through that body.

The invention relates to the technical field of circuit board cards, in particular to a double-BIOS and double-hard-disk processor board card which comprises a processor, a watchdog chip connected with the processor, two SPI FLASH storage chips, a single-chip microcomputer MCU and two starting hard disks. The two SPI FLASH storage chips are respectively connected with an SPI interface of the processor and two CS interfaces of the single chip microcomputer MCU in a one-to-one correspondence manner; the processor is connected with the single-chip microcomputer MCU through two GPIO ports. The single-chip microcomputer MCU is used for obtaining state codes of the processor through the two GPIO ports and switching the SPI FLASH storage chip used for receiving SPI signals of the processor based on the state codes. The two starting hard disks are configured to be a main hard disk and a standby hard disk which can be switched; and the main hard disk is connected to an SATA main channel of the processor.

A BLE-enabled electric jack system consisting of an STM32 processor board for controlling the motion and safety logic, a Bluetooth Low Energy module for receiving authenticated remote commands, a motor driver for controlling a high-torque jack motor, a rechargeable battery, a buzzer, and optical indicators, wherein the system raises and lowers a vehicle jack remotely with safety interlocks.

The invention discloses a multi-component industrial transmitter system, which comprises a transmitter main control circuit, a plurality of board card interfaces and a plurality of functional board card circuits, the transmitter main control circuit is respectively connected with each board card interface, and the board card interfaces are connected with the corresponding function board card circuits; the functional board card circuit comprises a processor, a board card insertion detection circuit, a power supply control circuit and a communication circuit; the board card insertion detection circuit is used for detecting whether a board card is inserted into a signal of the board card interface, the output end of the board card insertion detection circuit is connected with the input end of the processor, and the detected signal is sent to the input end of the processor; the output end of the processor is connected with the input end of the power supply control circuit, and the processor can send a switch control signal to the power supply control circuit. According to the multi-component industrial transmitter system provided by the invention, the functions of the system can be expanded, and meanwhile, the overall size of the transmitter is reduced; the transmitter is more powerful in function and flexible and changeable in application, and can cover all demand types of an industrial field.

The application provides a kind of PHM software function automation test equipment, the PHM software function automation test equipment includes host computer 1, host computer 2, host computer 3, analog comprehensive treater;The analog comprehensive treater includes 1394 interface board, general processing board A1, general processing board A2, general processing board A3, general processing board B, FC exchange board and network exchange board;General processing board A1, general processing board A2, general processing board A3 all include processor board and PF daughter card;1394 interface board includes processor board, PF daughter card and 4 node 1394 card;General processing board B includes processor board and PF daughter card;Network exchange board includes network exchange board 1 and network exchange board 2, network exchange board 1 is RapidIO switch, and network exchange board 2 is Ethernet switch;Host computer 3 contains FC monitoring card.

This invention discloses a redundancy control method, apparatus, and readable storage medium for a traction system. The traction system has at least a first central processing unit (CPU) and a second CPU that can be controlled. The redundancy control method includes: determining that the first CPU is the primary control unit, and the second CPU is the backup control unit; monitoring the operating status of the first CPU; if the first CPU fails, switching the second CPU to the primary control unit and activating the first CPU as the backup control unit. This invention solves the technical problem that a single CPU board has a high failure rate, which can easily lead to traction system failure.

The invention provides a multiprocessor data interaction simulation system and method, and the system comprises a CPU simulation calculation unit which comprises a multi-core processor, a data sharing memory and a PCIe communication card, the PCIe communication card comprises a first optical module interface and a PCIe interface, and the multi-core processor is connected with the PCIe interface through one of a high-speed PCIe bus or a slot; the FPGA processor board comprises an FPGA chip and a second optical module interface; the CPU simulation calculation unit is in communication connection with the at least one FPGA processor board through the first optical module interface and the second optical module interface; the plurality of CPU simulation calculation units are in communication connection through the first optical module interfaces; and the at least one CPU simulation calculation unit performs data interaction with the at least one FPGA processor board. The method has the beneficial effects that file configuration and data carrying time are not needed, and the data interaction efficiency is improved.

The embodiment of the invention provides an LCU system architecture with function safety, a control method and equipment, and is applied to the technical field of power electronics. The system architecture comprises at least two security hosts, IO board cards corresponding to the security hosts and a backboard parallel bus used for connecting the security hosts and the corresponding IO board cards. Wherein the security host comprises a processor, the IO board card is a non-intelligent board card without a processor, and the security host directly accesses and controls each input and output point location on the IO board card in an address mapping mode through the backboard parallel bus. According to the invention, the system is centralized to the security host, the IO board card is degraded into a pure and program-free logic combination circuit, the host directly controls each IO point location through the parallel bus in an address mapping mode, a processor on the IO board card is canceled, software development, protocol design and field configuration work related to the IO board card are fundamentally eliminated, the operation process is simplified, and the operation efficiency is improved. And potential software fault points are reduced.