5 results about "Processor board" patented technology

The application discloses a multi-ring network data transmission architecture, a data processing node control method and a storage medium, relates to the field of ring network architecture control, and comprises the following steps: each data processing node is configured with a first independent communication board card, a second independent communication board card, a first processor board card, a backboard and a memory; the first independent communication board card and the second independent communication board card are connected in series to two ring networks; the first independent communication board card, the second independent communication board card, the first processor board card and the memory are all hot-pluggable; and the first independent communication board card, the second independent communication board card and the memory are in communication connection with the first processor board card. According to the application, the first independent communication board card is connected in series to the first ring network, and the second independent communication board card is connected in series to the second ring network, so that data processing can still be maintained by another independent communication board card and the ring network where the independent communication board card is located when any independent communication board card fails, and the operation reliability of the double-ring network data transmission architecture adopted by the DCS platform is improved.

The embodiment of the application discloses a data reading and writing device, method, processor, board and computer equipment, and relates to the technical field of semiconductors. The device comprises a first memory, a second memory, a first request processing unit connected with the first memory, and a second request processing unit connected with the second memory; the first request processing unit is used for determining a first target request from a first candidate request, and reading and writing first data indicated by the first target request from the first memory, the first candidate request is used for requesting reading and writing the first memory, and the first request processing unit comprises an input port for receiving the first candidate request sent by a second processor; the second request processing unit is used for determining a second target request from a second candidate request, and reading and writing second data indicated by the second target request from the second memory, the second candidate request is used for requesting reading and writing the second memory, and the second request processing unit comprises an input port for receiving the second candidate request sent by a first processor.

The utility model relates to robot technical field, and disclose a kind of mainframe installation device for humanoid robot, including main body, the inside of main body is provided with mainframe installation mechanism, the mainframe installation mechanism includes equipment outer frame, the upper and lower ends of equipment outer frame are provided with threading slot, the both sides of threading slot are distributed with rubber pad strip, the inside top of equipment outer frame is provided with upper layer processor board card.This utility model provides protection to mainframe module part by the equipment outer frame carried in the inside of mainframe cavity, and the mainframe module part is composed of upper layer processor board card and lower power controller, respectively carried by slidable equipment box, and each group of equipment box two sides can be positioned by cooperating buckle, and the quick extraction and unlocking process of equipment box can be realized by cooperating button pressing, so that personnel do not need to remove element frequently in normal maintenance and maintenance operation, save removal step, facilitate maintenance and use.

A server system and a communication method of a server system are provided. The server system includes: at least one first processor board and a host server; the first processor board includes a first field programmable gate array chip and a first processor chip, the first field programmable gate array chip and the first processor chip being packaged and interconnected; the host server is configured to transmit host data to the first field programmable gate array chip through the switching network; and the first field programmable gate array chip is configured to process the host data, receive request data sent by the first processor chip, generate a communication protocol message according to processed host data and the request data, and transmit the communication protocol message to a target processor board through the switching network.