16 results about "Media access controller" patented technology

Provided in the present disclosure are an inter-processor communication method and apparatus for a system on chip, and a storage medium and an electronic device. The inter-processor communication method for a system on chip comprises: generating a communication request for performing inter-processor communication between a first processor and a second processor; determining a target media access controller on the basis of the communication request; on the basis of the communication request and the target media access controller, reading inter-processor communication data from a first address space corresponding to the first processor; and on the basis of the target media access controller, transmitting the inter-processor communication data to a second address space corresponding to the second processor, wherein the first address space and the second address space correspond to different address spaces in a memory. Thus, address spaces accessed by a first processor and a second processor are mutually independent, which can improve the security and stability of communication; in addition, parallel communication can be performed by means of a plurality of channels of a media access controller, such that large-data-volume inter-processor communication can be implemented, thereby improving the high efficiency and flexibility of inter-processor communication.

The invention relates to a forwarding control method and device, equipment and a medium, and relates to the technical field of communication. The method comprises the following steps: receiving a target data packet sent by a target terminal through a first gigabit Ethernet media access controller GMAC; wherein the first GMAC corresponds to a local area network side; under the condition that the target data packet is a first type of data packet, forwarding the target data packet through a second GMAC based on the forwarding table; wherein the first type of data packets are data packets which do not need to be processed by an application program and are forwarded based on a basic network protocol; the second GMAC corresponds to a wide area network side; under the condition that the target data packet is the second type of data packet, processing the target data packet through the application program, and forwarding the target data packet through the second GMAC after processing; wherein the second type of data packets are data packets which need to be forwarded after being processed by the application program. By adopting the method, intelligent forwarding control of the data packet can be realized.

The application discloses a chip, comprising: N core modules, N first path selectors, a first path control module, and N medium access controller (MAC) modules; N is a positive integer greater than 2; the output end of one first path selector is connected with one core module; the two input ends of the first first path selector are connected with the first MAC module and the second MAC module respectively; the two input ends of the Nth first path selector are connected with the Nth MAC module and the N-1th MAC module respectively; the three input ends of the mth first path selector are connected with the m-1th MAC module, the mth MAC module and the m+1th MAC module respectively; the first path control module is used for controlling the switch state of the first path selector when one core module is detected to be invalid, so that the first to N-1th MAC modules are respectively connected with one valid core module, and the core modules connected with different MAC modules are different.

The invention provides a network acceleration system and method based on a Loongson platform, and relates to the technical field of network cards, the system comprises a CPU core, a hardware logic module, a media access controller MAC and a port physical layer PHY, the CPU core is connected with one end of the media access controller MAC, and the hardware logic module is connected with the other end of the media access controller MAC. The other end of the media access controller MAC is connected with one end of the hardware logic module, and the other end of the hardware logic module is connected with the port physical layer PHY. According to the system, a special hardware logic module is integrated, so that a network data packet can be directly processed, and the burden of a CPU core is reduced. According to the hardware acceleration mode, the network data processing speed is remarkably increased, the delay of data transmission is reduced, and the method is particularly suitable for application scenes with high requirements for real-time performance.

A signal conversion method includes transmitting an Ethernet packet from an Ethernet media access controller to a transceiver, stacking an Ethernet media access control protocol layer corresponding to the Ethernet packet to a wireless communication protocol layer by using a protocol stack for generating a wireless communication packet after the transceiver receives the Ethernet packet, and generating a wireless communication signal according to the wireless communication packet.

A network device to function as an Access Point (AP) in a Wireless Local Area Network (WLAN) is provided. The AP is configured to acknowledge a data frame transmitted by a station (STA) in an uplink multi-user physical layer protocol data unit (UL MU PPDU). The AP includes one or more memories, a physical layer (PHY) processor, and a media access controller (MAC) processor. Each processor is coupled to the one or more memories, and is configured to receive the UL MU PPDU, decode an acknowledge (ACK) policy field within a data field of the UL MU PPDU, and determine whether an acknowledgement (ACK) policy indicated in the data field signals an implicit block acknowledgement (BlockAck) request. Responsive to a determination that the ACK policy indication signals an implicit acknowledgement policy, the AP is configured to transmit an ACK or BlockAck frame to the STA in either a single user (SU) or a multi user (MU) manner.

This invention proposes a congestion state transmission method and related apparatus, relating to the field of communication technology. A memory unit stores the current flow control function state and the pending flow control function state corresponding to each receiving module. Initially, both the current flow control function state and the pending flow control function state are in a disabled state. The memory unit can acquire state detection trigger events for the target receiving module. If the target current flow control function state and the target pending flow control function state of the target receiving module are different, a first congestion state is sent to the media access controller according to the target pending flow control function state, and the target current flow control function state is updated according to the target pending flow control function state. The first congestion state characterizes the congestion state of the target receiving module, and the target pending flow control function state is set by the central processing unit according to the flow control function setting instructions sent by the user, thus avoiding atomicity issues.

Method, system, and / or computer readable medium for providing enhanced diversity and reliability for a continued wireless connection including: establishing an upper upper medium access controller (UMAC) and a plurality of lower UMACs; discovering the upper UMAC by each of the plurality of lower UMACs; connecting a station (STA) actor to each of the plurality of lower UMACs; connecting each of the plurality of lower UMACs to the upper UMAC; and establishing a connection through the upper UMAC and each of the plurality of lower UMACs to the STA actor.

A pluggable medium access controller (MAC) layer includes (1) a physical (PHY) layer interface configured to interface the pluggable MAC layer with a PHY layer and (2) a plurality of MAC modules. Each MAC module of the plurality of MAC modules is configured to implement respective functionality of the pluggable MAC layer. In some embodiments, the plurality of MAC modules are implemented in software, and the pluggable MAC layer is accordingly virtually configurable.

Low-latency gigabit transceiver PHY-based signal switching for emulation, prototyping, and high performance computing (HPC) in a computing platform that includes multiple ICs, where a first one of the ICs includes functional circuitry, a receiver that receives a signal from a second one of the ICs, a transmitter that transmits outgoing data to a third one of the ICs, and a bypass circuit that provides an output of the receiver to one of the functional circuitry and the transmitter (e.g., based on a destination address). The bypass circuit may bypass the functional circuitry, and may further bypass a receive-side media access controller (MAC) and a transmit-side MAC. The IC may multiplex outgoing data to the transmitters. Selectable functions of PHY circuitry may be disabled in bypass mode. The ICs may include field-programmable gate arrays, which may be programmed to emulate respective partitions of a circuit design and / or to perform other functions.

The invention discloses a data transmission method, electronic equipment and a computer readable medium, and belongs to the technical field of data transmission, and the method comprises the steps: determining a current sent packet and a next sent packet based on a plurality of sequentially sorted sent packets corresponding to target data; according to the data sending mode of the target data, the transmission interface corresponding to the start mark of the current packet sending and the byte length of the current packet sending, determining a transmission interface corresponding to the end mark of the current packet sending; if the transmission interface corresponding to the ending mark of the current packet sending is a low-order interface, determining that the transmission interface corresponding to the starting mark of the next packet sending is a high-order interface; under the condition that the current sending packet is sent, the next sending packet is sent in the same clock period of sending the ending mark of the current sending packet, so that no idle frame exists between sending of the current sending packet and sending of the next sending packet, the data bandwidth is fully utilized, and the data transmission efficiency is improved. Therefore, line speed data transmission of the transmission interface of the two-section media access controller is realized.

The present invention discloses a token bucket algorithm current limiting system for DPU based on FPGA, which is directly deployed on FPGA and connected to the network card of the host through PCI-e interface; the system includes system configuration module, fast memory access module, Ethernet media access controller module and two groups of user logic frame modules. Aiming at the problem of traffic burst in system link, the present invention designs a flow control method according to the token bucket principle, so that the traffic in the link will not exceed the limit of the system transceiver, and can provide different strategies according to the type of data to meet user requirements, on the basis of ensuring the safe operation of the system, without wasting the original bandwidth, solving the instability factor brought by traffic burst to DPU; it has the advantages of realizing multi-path and different data packet current limiting strategies, and there is no other dependent hardware, algorithm, protocol resources and requirements in deployment, and it can be directly used on FPGA.

The invention discloses a network time delay self-calibration method, which is applied to a processing unit of a system on chip, the system on chip at least comprises the processing unit and a programmable logic unit, the processing unit comprises a media access controller, and the programmable logic unit is configured with a time delay module. An interface signal of the media access controller is transmitted to the programmable logic unit through an interconnection resource between the processing unit and the programmable logic unit, and the time delay module calibrates network time delay of the interface signal according to an optimal time delay point of the configured interface signal. The network time delay self-calibration method comprises the following steps: after the system on chip and external equipment establish network connection and are in the same network segment, executing a preset time delay calibration strategy to obtain an optimal time delay point of an interface signal, and configuring a time delay module according to the optimal time delay point. According to the method and the device, the technical problems of difficulty in time delay configuration and poor robustness caused by internal routing uncertainty of the FPGA are solved, the time delay calibration efficiency is remarkably improved, and the technical threshold of debugging requirements is reduced.

The present invention discloses a cell construction method, device, base station, medium and product, which are applied to a card chip, the card chip includes a message forwarding kernel, a time synchronization kernel and eight service kernels, and the method includes: after power-on, initializing each kernel, physical layer and media access controller based on a pre-configured version file; sending a request message to the physical layer through the media access controller; feeding back the current state to the media access controller through the physical layer based on the request message; when the preset conditions are met, dividing the service kernel into service kernel groups according to the pre-configured version file, configuring the cell-related parameters for each service kernel group, providing cells under different mobile communication technologies through different service kernel groups; feeding back the configuration information to the media access controller; executing the scheduling according to the configuration information, and completing the establishment of the cell. By deploying all the physical layer protocol stacks on the card chip, the establishment of different cells is realized at the same time, with low power consumption and small size.

A pluggable medium access controller (MAC) layer includes (1) a physical (PHY) layer interface configured to interface the pluggable MAC layer with a PHY layer and (2) a plurality of MAC modules. Each MAC module of the plurality of MAC modules is configured to implement respective functionality of the pluggable MAC layer. In some embodiments, the plurality of MAC modules are implemented in software, and the pluggable MAC layer is accordingly virtually configurable.

The invention relates to an Ethernet data transmission method and system, communication equipment and a readable storage medium. The method is applied to an Ethernet packet manager, an Ethernet media access controller, a target memory and a message accelerator are arranged outside the Ethernet packet manager, and the method comprises the following steps: reading first descriptor information from the target memory under the condition that an uplink transmission interrupt signal of the Ethernet media access controller is received, reading second descriptor information from an Ethernet packet manager according to the first descriptor information; determining to-be-transmitted data according to the first descriptor information and the second descriptor information, and transmitting the to-be-transmitted data to a message accelerator; and third descriptor information returned by the message accelerator is obtained, the third descriptor information is written back to the target memory, and the third descriptor information is obtained after the message accelerator processes the to-be-transmitted data and then releases the to-be-transmitted data. By adopting the method, the data transmission progress can be accelerated.