Network acceleration system and method based on Loongson platform
By designing a network acceleration system on the Longxin platform, the hardware logic module uses the network data packet to solve the problem of large CPU burden when processing high -speed data, and achieves more efficient network data processing and lower latency.
Patent Information
- Application Number
- CN202411371240.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-29
- Publication Date
- 2025-01-21
AI Technical Summary
When traditional network cards process high-speed and large-capacity network data, they need to occupy a large amount of CPU resources, resulting in increased CPU burden and network performance impact.
Design a network acceleration system based on the Loongson platform, including the CPU core, hardware logic module, media access controller MAC and port physical layer PHY. The hardware logic module directly processes network data packets to reduce the burden on the CPU.
Through hardware acceleration, the speed of network data processing is significantly improved and the delay of data transmission is reduced. It is suitable for application scenarios with high real-time requirements.
Smart Images
Figure CN119341852A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of network card technology, and in particular to a network acceleration system and method based on a Loongson platform. Background Art
[0002] With the rapid development of information technology and the increasing popularity of Internet applications, the demand for network bandwidth has gradually increased from the traditional gigabit (1G) network to the current 10-gigabit (10G) and even 100-gigabit (100G) network technology, marking that the field of network communications is undergoing unprecedented changes. This bandwidth leap has not only greatly improved the speed and efficiency of data transmission, but also provided a solid network foundation for high-bandwidth applications such as cloud computing, big data, high-definition video transmission, and remote real-time interaction. The continuous improvement of network bandwidth has also posed a more severe challenge to network data processing capabilities. In the process of network communication, the efficient reception and processing of data packets is a key link to ensure stable and efficient network performance.
[0003] In traditional data processing, this task is mainly completed by the media access control layer (MAC) and the physical layer (PHY) in the network interface card (NIC, usually referred to as the network card). The MAC layer is responsible for the data frame encapsulation and decapsulation, address recognition and error detection of the data link layer, while the PHY layer is responsible for the transmission and reception of data on the physical medium. The two work together to receive network data packets from the physical line and convert them into a data format that the CPU can recognize. However, with the rapid increase in network bandwidth, the data traffic in the network has also increased exponentially, which has caused the processing of network data packets to become a resource-intensive task. When processing high-speed, large-capacity network data, the traditional network card architecture often needs to occupy a large amount of CPU resources to perform advanced processing operations such as data packet analysis, filtering, and forwarding. This not only increases the burden on the CPU, but may also affect the overall network performance due to processing delays. Summary of the invention
[0004] In view of the above problems, the present application provides a network acceleration system and method based on the Loongson platform, including the following contents:
[0005] In a first aspect, the present application provides a network acceleration system based on the Loongson platform, the system comprising:
[0006] CPU core, hardware logic module, media access controller MAC and port physical layer PHY;
[0007] The CPU core is connected to one end of the media access controller MAC;
[0008] The other end of the media access controller MAC is connected to one end of the hardware logic module;
[0009] The other end of the hardware logic module is connected to the port physical layer PHY.
[0010] Optionally, the hardware logic module is a programmable logic device;
[0011] The programmable logic device is a field programmable gate array or an application specific integrated circuit.
[0012] Optionally, the hardware logic module includes a traffic management module, which is used to process data packets obtained from the physical layer PHY of the port, wherein the data packets carry multiple network protocol information;
[0013] The multiple network protocol information includes source IP address, destination IP address, port number, and protocol type.
[0014] Optionally, the traffic management module is used to pre-process the data packet obtained from the port physical layer PHY, and the pre-processing includes:
[0015] Packet filtering, packet concatenation, packet smoothing, and adding VLAN to packets.
[0016] Optionally, the hardware logic module includes a bypass mode. When a system failure occurs or the processing flow of the traffic management module needs to be bypassed, the data packets obtained from the port physical layer PHY will be directly transmitted through the line interface without being processed by the traffic management module.
[0017] Optionally, the system is applied to the Loongson platform to improve data processing performance.
[0018] In a second aspect, the present application provides a network acceleration method based on the Loongson platform, the method comprising:
[0019] The data packets acquired by the port physical layer PHY are transmitted to the hardware logic module through the data interface;
[0020] After the hardware logic module performs data preprocessing on the data packet, the processed data packet is sent to the media access controller MAC through the data interface, and the media access controller MAC then transmits the data to the CPU.
[0021] Optionally, the hardware logic module is a programmable logic device;
[0022] The programmable logic device is a field programmable gate array or an application specific integrated circuit.
[0023] Optionally, the method further includes:
[0024] Acquire a data packet from the physical layer PHY of the port, wherein the data packet carries a variety of network protocol information;
[0025] The multiple network protocol information includes source IP address, destination IP address, port number, and protocol type.
[0026] Optionally, after obtaining the data packet from the port physical layer PHY, the method further includes:
[0027] Preprocessing the data packet obtained from the port physical layer PHY, the preprocessing comprising:
[0028] Packet filtering, packet concatenation, packet smoothing, and adding VLAN to packets.
[0029] Optionally, the hardware logic module includes a bypass mode. When a system failure occurs or the processing flow of the traffic management module needs to be bypassed, the data packets obtained from the port physical layer PHY will be directly transmitted through the line interface without being processed by the traffic management module.
[0030] Optionally, the system is applied to the Loongson platform to improve data processing performance.
[0031] In a third aspect, the present application provides a device comprising a memory and a processor, wherein the memory is used to store instructions or codes, and the processor is used to execute the instructions or codes, so that the device executes the network acceleration method based on the Loongson platform introduced in any implementation method of the aforementioned second aspect.
[0032] In a fourth aspect, the present application provides a computer-readable storage medium, in which codes are stored. When the codes are executed, the device executing the codes implements the network acceleration method based on the Loongson platform introduced in any implementation of the aforementioned second aspect.
[0033] The present application provides a network acceleration system based on the Loongson platform, the system includes a CPU core, a hardware logic module, a media access controller MAC and a port physical layer PHY, the CPU core is connected to one end of the media access controller MAC, the other end of the media access controller MAC is connected to one end of the hardware logic module, and the other end of the hardware logic module is connected to the port physical layer PHY. By integrating a special hardware logic module, the system can directly process network data packets, reducing the burden on the CPU core. This hardware acceleration method significantly improves the speed of network data processing and reduces the delay of data transmission, and is particularly suitable for application scenarios with high real-time requirements. BRIEF DESCRIPTION OF THE DRAWINGS
[0034] In order to more clearly illustrate the technical solutions in this embodiment or the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.
[0035] Figure 1 A schematic diagram of the structure of a network acceleration system based on the Loongson platform provided in an embodiment of the present application;
[0036] Figure 2 A schematic diagram of the internal structure of a network acceleration system based on the Loongson platform provided in an embodiment of the present application;
[0037] Figure 3 A flowchart of a network acceleration method based on the Loongson platform provided in an embodiment of the present application. DETAILED DESCRIPTION
[0038] As described in the background technology of this application, the traditional network interface card (NIC, usually referred to as a network card) performs data processing through the collaboration of the media access control layer (MAC) and the physical layer (PHY). The MAC layer is responsible for the data frame encapsulation and decapsulation, address recognition and error detection of the data link layer, while the PHY layer is responsible for the transmission and reception of data on the physical medium. The two work together to receive network data packets from the physical line and convert them into a data format that can be recognized by the CPU. However, with the sharp increase in network bandwidth, the data traffic in the network has also increased exponentially, which has caused the processing of network data packets to become a resource-intensive task. When processing high-speed, large-capacity network data, the traditional network card architecture often needs to occupy a large amount of CPU resources to perform advanced processing operations such as data packet analysis, filtering, and forwarding, which not only increases the burden on the CPU, but may also affect the overall network performance due to processing delays.
[0039] In order to solve the above technical problems, an embodiment of the present application provides a network acceleration based on the Loongson platform, the system comprising: a CPU core, a hardware logic module, a media access controller MAC and a port physical layer PHY, the CPU core is connected to one end of the media access controller MAC, the other end of the media access controller MAC is connected to one end of the hardware logic module, and the other end of the hardware logic module is connected to the port physical layer PHY.
[0040] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.
[0041] Figure 1 A schematic diagram of the structure of a network acceleration system based on the Loongson platform provided in an embodiment of the present application, including: a CPU core, a hardware logic module, a media access controller MAC and a port physical layer PHY;
[0042] The CPU core is connected to one end of the media access controller MAC; the other end of the media access controller MAC is connected to one end of the hardware logic module, and the other end of the hardware logic module is connected to the port physical layer PHY.
[0043] The CPU core (Central Processing Unit Core) is the core of the computer system, responsible for executing program instructions and processing data. In a multi-core processor, a CPU can contain multiple cores, each of which can perform tasks independently, thereby increasing the overall processing speed.
[0044] In the network acceleration system based on the Loongson platform of the present application, the CPU core is responsible for running the operating system and application software, while managing and scheduling network resources, including tasks such as receiving, processing and sending data packets.
[0045] A hardware logic module refers to a hardware circuit or chip specifically designed to perform a specific logic function. These modules are usually designed using a hardware description language (HDL) and are optimized to perform high-speed, low-power, and reliable computing tasks. In the network acceleration system of the present application, the hardware logic module is responsible for handling complex and repetitive tasks related to network communications, such as data packet diversion, filtering, encryption / decryption, compression / decompression, etc. If these tasks are handled by CPU software, they will take up a lot of CPU resources and affect system performance. By offloading these tasks to the hardware logic module, the network processing speed and throughput can be significantly improved while reducing the CPU load.
[0046] The media access controller is a key component in the network interface card (NIC), which is responsible for processing communication protocols at the data link layer, such as the Ethernet protocol. The MAC address is a unique identifier for a network device in the network, and is used to send and receive data frames at the data link layer. In the network acceleration system based on the Loongson platform in the embodiment of the present application, the MAC controller is responsible for receiving data frames from the network, and parsing, checking and forwarding them as needed. At the same time, it is also responsible for sending data frames from the CPU or hardware logic module to the network. The MAC controller works closely with the hardware logic module to ensure the correct and efficient transmission of network data.
[0047] The port physical layer (Physical Layer, PHY) is responsible for handling the physical connection and signal transmission of network devices. The PHY chip is a key component for realizing the functions of the physical layer. It is responsible for converting digital signals into analog signals (or vice versa) for transmission on network media (such as twisted pair, optical fiber, etc.). In the network acceleration system of the present application, the PHY chip is connected to the hardware logic module and is responsible for converting the processed network data into a signal form suitable for transmission on the physical medium. At the same time, it is also responsible for receiving data signals from the network medium and converting them into digital signals for further processing by the hardware logic module. The performance of the PHY chip directly affects the speed and quality of network transmission.
[0048] Combine the following Figure 2 The specific structure of the network acceleration system based on the Loongson platform in this application is introduced. Figure 2 A schematic diagram of the internal structure of a network acceleration system based on the Loongson platform provided in an embodiment of the present application.
[0049] In one implementation of the embodiment of the present application, the hardware logic module is a programmable logic device, and the programmable logic device is a field programmable gate array or an application-specific integrated circuit. Figure 2 The programmable logic device is a field programmable gate array as an example, which includes:
[0050] Field Programmable Gate Array (FPGA), as a programmable logic device, is used to implement complex logic and data processing functions, such as traffic shaping, packet modification, etc. FPGA includes Traffic Manage (traffic management module): as the core module of the system, it is responsible for processing data traffic from different sources, including managing the transmission of data streams between the host (HOST_MAC) and the line interface (LINE_MAC). Interact with VLAN (virtual local area network) and CTRL (control) modules to perform operations such as traffic filtering and priority control. The traffic management module is specifically used for traffic filtering, priority control, load balancing and QoS (quality of service) management, etc., to ensure that data packets of key applications can be forwarded first. CLOCK_GEN provides clock signals for FPGA and the entire system to ensure that all parts work synchronously.
[0051] The traffic management module is used to process the data packets obtained from the port physical layer PHY, and the data packets carry multiple network protocol information; the multiple network protocol information includes source IP address, destination IP address, port number, and protocol type. Specifically, the source IP address refers to the sender address of the data packet, which is used to identify the source of the data packet. The destination IP address refers to the destination address of the data packet, which is used to correctly route the data packet to the receiver. The port number is used to distinguish different applications or services on the same device to ensure that the data packet can be sent to the correct application or service. The protocol type refers to the type of network protocol used by the data packet, such as TCP, UDP, etc., so that the receiver can parse and process it according to the corresponding protocol. After receiving the data packet from the port physical layer (PHY), the traffic management module parses the network protocol information such as the source IP address, destination IP address, port number and protocol type in the data packet. Then, according to the network protocol and policy, the data packet is classified and assigned a corresponding priority. According to the network bandwidth, load conditions and priority policy, the sending rate and queue length of the data packet are dynamically adjusted. The processed data packet is forwarded to the next hop address or destination address.
[0052] Processor, in the embodiment of the present application, LS2K1000 is taken as an example, that is, Loongson 2K1000 is used as the processor. The processor provides high-speed data transmission capability for the host and is one of the main paths for data to enter the system. It is connected to TrafficManage in the FPGA as a bridge for data exchange. The processor also includes gigabit media access controllers GMAC#0 and GMAC#1, where GMAC#0 and GMAC#1 are connected to the FPGA via a reduced gigabit media independent interface (Reduced Gigabit Media Independent Interface, RGMII). As a logical interface unit (LogicalInterface Organization), LIO is responsible for processing or forwarding specific data or control signals.
[0053] The port physical layer PHY, including 88E1111 Phy#0 and 88E1111 Phy#1, is connected to the FPGA through the Reduced Gigabit Media Independent Interface (RGMII). It is responsible for receiving data signals from the network medium and converting them into digital signals for further processing by the hardware logic module.
[0054] In an implementation of the embodiment of the present application, the traffic management module is used to pre-process the data packet obtained from the port physical layer PHY, and the pre-processing includes:
[0055] Packet filtering, packet concatenation, packet smoothing, and adding VLAN to packets.
[0056] Packet filtering is a network security technology that checks packets passing through the network and allows or denies them based on a preset set of rules. Packet filtering can prevent malicious packets (such as viruses, worms, Trojan horses, etc.) from entering the network, protect the network from attacks, reduce unnecessary network traffic, and improve the utilization of network bandwidth.
[0057] Packet splicing refers to reassembling a packet that has been split into multiple fragments due to network transmission limitations into a complete packet. This ensures that the receiver can receive the complete packet instead of the fragmented fragments. This can reduce the additional overhead caused by packet segmentation (such as header information duplication).
[0058] Packet smoothing is a traffic shaping technology that adjusts the rate at which packets are sent to reduce network congestion and jitter.
[0059] VLAN (Virtual Local Area Network) is a technology that logically divides LAN devices into segments. Each VLAN is an independent broadcast domain. By adding a VLAN tag to the header of a data packet, the tag contains the VLAN identifier (VID) and other related information. Data packets are forwarded based on the VLAN tag to ensure that they are only sent to devices belonging to the same VLAN.
[0060] In one implementation of the embodiment of the present application, the hardware logic module includes a bypass mode. When the system fails or needs to bypass the processing flow of the traffic management module, the data packet obtained from the port physical layer PHY will be directly transmitted through the line interface without being processed by the traffic management module.
[0061] Bypass mode means that when a system fails or certain processing procedures need to be bypassed under certain circumstances, data packets can be transmitted directly through the line interface without passing through the original processing module (such as the traffic management module). This mechanism ensures that network communications can continue to be maintained when a network device or system fails, avoiding complete interruption. By designing a dedicated bypass channel and switching mechanism in the network device, when the system detects a failure or receives a bypass instruction, the data packet is automatically directed to the bypass channel for transmission.
[0062] In one implementation of the embodiment of the present application, the system is applied to the Loongson platform to improve data processing performance.
[0063] Figure 3 A flowchart of a network acceleration method based on the Loongson platform provided in an embodiment of the present application. Figure 3 As shown, the network acceleration method based on the Loongson platform provided in the embodiment of the present application may include:
[0064] S301 . The data packet acquired by the port physical layer PHY is transmitted to the hardware logic module through the data interface.
[0065] S302: After the hardware logic module performs data preprocessing on the data packet, the processed data packet is sent to the media access controller MAC through the data interface, and the media access controller MAC then transmits the data to the CPU.
[0066] In one implementation of the embodiment of the present application, the hardware logic module is a programmable logic device;
[0067] The programmable logic device is a field programmable gate array or an application specific integrated circuit.
[0068] In one implementation of the embodiment of the present application, the method further includes:
[0069] Acquire a data packet from the physical layer PHY of the port, wherein the data packet carries a variety of network protocol information;
[0070] The multiple network protocol information includes source IP address, destination IP address, port number, and protocol type.
[0071] In an implementation manner of the embodiment of the present application, after obtaining the data packet from the port physical layer PHY, the method further includes:
[0072] Preprocessing the data packet obtained from the port physical layer PHY, the preprocessing comprising:
[0073] Packet filtering, packet concatenation, packet smoothing, and adding VLAN to packets.
[0074] In one implementation of the embodiment of the present application, the hardware logic module includes a bypass mode. When the system fails or needs to bypass the processing flow of the traffic management module, the data packet obtained from the port physical layer PHY will be directly transmitted through the line interface without being processed by the traffic management module.
[0075] In one implementation of the embodiment of the present application, the system is applied to the Loongson platform to improve data processing performance.
[0076] The embodiments of the present application also provide corresponding devices and computer storage media for implementing the solutions provided by the embodiments of the present application.
[0077] The device includes a memory and a processor, the memory is used to store instructions or codes, and the processor is used to execute the instructions or codes so that the device executes the method described in any embodiment of the present application.
[0078] The computer storage medium stores codes, and when the codes are executed, a device executing the codes implements the method described in any embodiment of the present application.
[0079] Through the description of the above implementation methods, it can be known that those skilled in the art can clearly understand that all or part of the steps in the above-mentioned embodiment method can be implemented by means of software plus a general hardware platform. Based on such an understanding, the technical solution of the present application can be embodied in the form of a software product, which can be stored in a storage medium, such as a read-only memory (ROM) / RAM, a disk, an optical disk, etc., including a number of instructions for a computer device (which can be a personal computer, a server, or a network communication device such as a router) to execute the methods described in each embodiment of the present application or some parts of the embodiments.
[0080] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.
[0081] It should also be noted that the various embodiments in this specification are described in a progressive manner, and the same and similar parts between the various embodiments can refer to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the device and system embodiments, since they are basically similar to the method embodiments, the description is relatively simple, and the relevant parts can refer to the partial description of the method embodiments. The device and system embodiments described above are merely schematic, in which the units described as separate components may or may not be physically separated, and the components indicated as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the scheme of this embodiment. Ordinary technicians in this field can understand and implement it without paying creative labor.
[0082] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed in the present application should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.
Claims
1. A network acceleration system based on the Loongson platform, characterized in that: The system comprises: CPU core, hardware logic module, media access controller MAC and port physical layer PHY; The CPU core is connected to one end of the media access controller MAC; The other end of the media access controller MAC is connected to one end of the hardware logic module; The other end of the hardware logic module is connected to the port physical layer PHY.
2. The network acceleration system according to claim 1, characterized in that: The hardware logic module is a programmable logic device; The programmable logic device is a field programmable gate array or an application specific integrated circuit.
3. The network acceleration system according to claim 2, characterized in that: The hardware logic module includes a traffic management module, which is used to process data packets obtained from the port physical layer PHY, wherein the data packets carry multiple network protocol information; The multiple network protocol information includes source IP address, destination IP address, port number, and protocol type.
4. The network acceleration system according to claim 3, characterized in that: The traffic management module is used to process the data packets obtained from the port physical layer PHY for preprocessing, and the preprocessing includes: Packet filtering, packet concatenation, packet smoothing, and adding VLAN to packets.
5. The network acceleration system according to claim 3, characterized in that: The hardware logic module includes a bypass mode. When a system failure occurs or the processing flow of the traffic management module needs to be bypassed, the data packet obtained from the port physical layer PHY will be directly transmitted through the line interface without being processed by the traffic management module.
6. The network acceleration system according to any one of claims 1 to 5, characterized in that: The system is applied to the Loongson platform to improve data processing performance.
7. A network acceleration method based on the Loongson platform, characterized in that: The network acceleration system based on the Loongson platform as described in any one of claims 1 to 6 above, the method comprising: The data packets acquired by the port physical layer PHY are transmitted to the hardware logic module through the data interface; After the hardware logic module performs data preprocessing on the data packet, the processed data packet is sent to the media access controller MAC through the data interface, and the media access controller MAC then transmits the data to the CPU.
8. The method according to claim 7, characterized in that The hardware logic module is a programmable logic device; The programmable logic device is a field programmable gate array or an application specific integrated circuit.
9. A computing device, characterized in that The computing device includes: a memory and a processor; The memory is used to store computer programs; The processor is used to implement the method according to any one of claims 7 to 8 when executing the computer program.
10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the method according to any one of claims 7 to 8 is implemented.