Parallel Pattern Detection Engine

Abstract

A parallel pattern detection engine (PPDE) comprise multiple processing units (PUs) customized to do various modes of pattern recognition. The PUs are loaded with different patterns and the input data to be matched is provided to the PUs in parallel. Each pattern has an Opcode that defines what action to take when a particular data in the input data stream either matches or does not match the corresponding data being compared during a clock cycle. Each of the PUs communicate selected information so that PUs may be cascaded to enable longer patterns to be matched or to allow more patterns to be processed in parallel for a particular input data stream.

Description

CROSS REFERENCE TO RELATED APPLICATIONS [0001] The present invention is related to the following U.S. patent applications which are incorporated herein by reference: [0002] Ser. No. ______ (Attorney Docket No. RPS920030020US1) entitled “A Configurable Bi-Directional Bus For Communicating Between Autonomous Units” filed ______; and [0003] Ser. No. ______ (Attorney Docket No. RPS920030037US1) entitled “Intrusion Detection Using A Network Processor And A Parallel Pattern Detection Engine” filed ______.TECHNICAL FIELD [0004] The present invention relates in general to methods and systems for performing fast partial or exact pattern matching. BACKGROUND INFORMATION [0005] Recognizing patterns within a set of data is important in many fields, including speech recognition, image processing, seismic data, etc. Some image processors collect image data and then pre-process the data to prepare it to be correlated to reference data. Other systems, like speech recognition, are real time where th...

AI Technical Summary

Benefits of technology

[0011] A parallel pattern detection engine comprises a large number of small processing units building blocks that perform pattern detection. These processing units have multiple modes of pattern detection and each has memory for storing patterns. A large parallel interface bus supplies input data to an input buffer. Selected input data is coupled in parallel to each processing unit so that each processing unit compares, in parallel, input data received on the parallel bus. Each processing unit is also coupled to a parallel address bus so that detection pattern data may be selectively loaded into each processing unit. The addresses of each processing unit comprises its identification (ID). Processing units that generate a match of its detection pattern to a pattern in the input data, according to its specific mode, have their corresponding ID forwarded by an ID selection unit to an output buffer. The data from the output buffer is coupled to the interface bus for sending results of a particular input data stream comparison. Each of the processing units has a “chaining” or cascading communication interface that allows a particular processing unit to be coupled to its corresponding adjacent processing units for generating larger detection patterns greater than a single PU can handle or for determining specific types of pattern matching. The parallel input bus structure and the chaining communication interface facilitate adding groups of the parallel pattern detection engines to create larger systems for speed or for handling a larger number of patterns or for both purposes.

Problems solved by technology

In non-aligned data streams, there are some situations where patterns may be missed if only a single byte-by-byte comparison is implemented.

Since a library of RPs may be quite large, the processing required may be considerable.

Processing in small parallel processing units may be limited by the storage size required for the RPs.

Portable, inexpensive processing systems for chemical analysis, biological analysis, etc., may also be limited by the amount of storage needed to quickly process large numbers of RPs.

Pattern detection or recognition is a bottleneck in many applications today and software solutions cannot achieve the necessary performance.

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