85results about How to "Avoid access violations" patented technology

The invention discloses an intelligent vision based vehicle law-violation parking detection system and method. The detection system is that the output end of a visual sensor node is connected with an image processing terminal device and a video database management device, the image processing terminal device is connected with the video database management device, the image processing terminal device and the video database management device are jointly connected with a database, the database is connected with a geographical information system, the visual sensor node, the image processing terminal device, the video database management device, the database and the geographical information system form an image processing private network, the image processing private network is connected with a data private network through a safety access platform, a client-side management system is arranged in the data private network, automatically detects law-violation parking behaviors of vehicles, automatically records law-violation videos and performs timely processing, 'second accidents' caused by processing lag are avoided, data safety is ensured, data integrity and confidentiality can be effectively protected, and the intelligent vision based vehicle law-violation parking detection system and method have good application prospect.

A system used for connecting with the intelligent electronic equipment in the transformer substation, so as to realize the tele-mechanics transmission of ''four remote'' date for the equipment in the transformer substation. The system adds a communication layer between the equipment in the isolated layer and the monitored control system of the transformer substation. The communication layer adopts the communication supervisor which is constituted by the high performance embedded system. Simultaneously, the data acquisition for the site equipment RS 485channel is completed and the communication protocol conversion is finished for the Ethernet transmission. Also, both the two-equipment and the double-channel redundancy communication can be realized to improve the reliability of data acquisition and communication as well as guarantee the reliability and the real time of the electric system's tele-mechanic data transmission, so as to solve such problems as the access conflict among a plurality of the primary stations at RS 485 port of the intelligent electronic equipment in the isolated layer as well as the remote control limits exist in a plurality of the monitored control system. Therefore, an effective access method is provided for the equipment in the middle isolated layer of the transformer substation's automation system to directly go through the Ethernet for completing the monitoring function.

The invention discloses a multichannel NAND flash parallel memory controller and aims to provide a memory controller which is capable of providing larger aggregation bandwidth and has high data reading and writing reliability. The multichannel NAND flash parallel memory controller comprises a switching structure module and n bottom-layer memory controllers, wherein the switching structure module comprising a request queue, a transmission arbitration member and a crossbar switch is used for carrying out transmission arbitration on requests of a plurality of channels; each bottom-layer memory controller consisting of a master control logic module and an ECC (Error Checking and Correcting) module is used for generating a control signal meeting a chip time sequence requirement and carrying out ECC on data; the master control logic module comprises a data buffer, a third register group and a master controller, and the ECC module comprises an ECC master control logic, an ECC check code generator and an error address generator. By using the multichannel NAND flash parallel memory controller, a parallel access mechanism of a multichannel NAND flash chip is realized, the aggregation bandwidth is effectively increased, the requirement of data intensive calculation for large bandwidth is met, an ECC function is realized, and the data reliability is improved.

The invention discloses a multicore architecture supporting dynamic binary translation, aiming to solve the problems of Cache access conflict, main memory conflict and the like during dynamic binary translation. The multicore architecture comprises a plurality of processor cores, a plurality of primary Caches, a plurality of translation cache units, a secondary Cache and a main memory controller,wherein the primary Caches and the translation cache units are private for each processor core; the secondary Cache and the main memory controller are shared by all the processor cores; each translation cache unit comprises a communication control unit, a cache management unit and a data memory unit; the communication control unit comprises a multi-channel selector, a communication control unit controller, a transmission bus and three registers; the cache management unit comprises a page replacement component and a cache management control component; and the data memory unit comprises a source architecture binary code cache area, a target architecture binary code cache area and a page mapping table. The multicore architecture has the following technical effects: the data access latency isreduced, the translation throughput is high and the Cache access conflict is less.

An apparatus for an idle mode terminal is configured to perform a method for operating the idle mode terminal in a Machine to Machine (M2M) communication system. A paging message is received from the base station during a paging listening interval. The Apparatus determines whether an indicator indicating receipt of multicast group data is included in the paging message. When the indicator indicating the receiving of multicast group data is included, data transmitted via a downlink resource that uses an identifier mask of a multicast group to which a terminal belongs is received. Thereafter, a paging non-listening interval is entered.

The invention relates to an FPGA-based high-speed adaptive DVB-S2 LDPC decoder and a decoding method. the method comprises steps: (1) matrix transformation is carried out, the generated left matrix has a quasi-cyclic structure, and the right matrix is a new matrix for a triangle-to-dual-diagonal (RTS) sub matrix; (2) RAM and iteration times are initialized; (3) the two parts of matrixes complete variable node information updating and data write back; (4) node information updating and write back are verified, a syndrome vector s is calculated, and one is added to the iteration times iter; (5) if the syndrome vector s is equal to 0 or the maximum iteration times are reached, a sixth step is carried out, or otherwise, the third step is carried out for next-round iteration processing; and (6) a decoding judgment bit is read, and a decoding codeword is outputted.

The invention relates to a quasi-cyclic low-density parity-check (LDPC) code construction method. A quasi-cyclic LDPC code to be constructed is represented by a tree graph model Tanner graph, and the quasi-cyclic check matrix parameter is that the size of a basis matrix is m * n, the size of a Block matrix is p * p, and basis matrix variable nodal point dimensionality distribution is represented by dv. The method comprises the follow steps: (1) determining check nodal point homogenization dimensionality distribution (dc) according to the basis matrix variable nodal point dimensionality distribution (dv) and adding all the n variable nodal points to the Tanner graph according to the dimensionality distribution (dc); (2) adding m check nodal points to the Tanner graph line by line and selecting pre-selected variable nodal points, determining the variable nodal points reaching a weight preset value according to side boundary weight and serving as an alternative set, and obtaining the variable nodal points with avoiding degree (ADeg) equal to or larger than delay (DLY) in a screening mode from the alternative set; and (3) determining the side boundary weight in the Tanner graph according to the points obtained from the step (2), adding corresponding sides to the Tanner graph, obtaining the quasi-cyclic LDPC code according to the Tanner graph, and achieving the construction of the quasi-cyclic LDPC code.

The invention discloses an accessing method for real-time processing a shared resource in a system and a real-time processing system. The method comprises the following steps: starting a thread of the real-time processing system, wherein the real-time processing system comprises a plurality of input preparation units (IPU), every IPU comprises a content provider (CP) thread and an icon file (ICO) thread; the relative priorities between the threads in the IPU is that the priority level of the CP thread is greater than that of the ICO thread; receiving a configuring order of a user input and buffering the configuring order in a command descriptor block (CDB), the priority level of the CDB thread is less than that of the ICO thread; and in every IPU, the shared resource can be accessed according to the priority level of every thread. Through the invention, the problem that the system hanging is easy to be caused by semaphore locking method is resolved, the stability and the reliability of the system are enhanced.

The invention discloses a method for avoiding modbus real-time database access conflict. The method comprises the following steps of: performing update operation on a database by a console in a modbus master station, caching an instruction of the update operation in an instruction buffer area, and comparing the instruction with the previous buffer instruction. Only when the instruction is changed, the instruction is updated to the database; the instruction is stored by an instruction buffer; and in a cyclic list of the modbus master station, each update operation instruction aiming at the database has the corresponding instruction buffer, and the buffers are cleared when starting and before entering a cycle. The method can ensure that the sent instruction is accurately executed when two consoles have only one sending instruction in a multi-console modbus system, and the real-time database access conflict is solved.

The embodiment of the invention provides a network device and a physical layer address allocation method. The network device comprises a CPU, a CPLD and a plurality of expansion card slot positions; the CPLD monitors whether expansion cards are inserted in the expansion card slot positions, a first indicating position corresponding to the first expansion card slot position with an inserted expansion card in a register of the CPLD is set as an identifier used for indicating that the expansion card has been inserted; the CPU determines the identifier of the first expansion card slot position, determines a first PHY address corresponding to the identifier of the first expansion card slot position according to a pre-stored corresponding relation between the identifier of the first expansion card slot position and the PHY address, and sets a second indicating position corresponding to the first expansion card slot position in the CPLD as the first PHY address; and the CPLD obtains the firstPHY address from the register and allocates the first PHY address to a PHY chip contained in the expansion card inserted in the first expansion card slot position.

A memory access controller and a method of accessing a memory are provided. According to the invention, the program and the data address are decoupled through the address table. According to the storage access controller and the storage control method, wrong data access is avoided through the permission table, access conflicts are avoided through the state table, wrong data reading is avoided through verification, data reliability is improved through backup, and various technical means are comprehensively applied to perfect the storage access controller and the storage control method. The storage access controller comprises an address table, a permission table, a state table and a reader-writer, the address table records data block addresses, the permission table records the access permission of the threads to the data blocks, and the state table records the states of the data blocks. The reader-writer receives the access request and executes the received access request according to the configuration information of the address table, the authority table and the state table.

The invention provides an interface access method, a display device and electronic equipment, and relates to the technical field of display. The method comprises the following steps: when a screen menu board card receives a viewing instruction of a microphone volume interface, periodically accessing the interface according to a preset access mode, the preset access mode comprising, in each period,after each execution of an interface access operation on the microphone volume data for a first preset number of times, executing an interface access operation on the video channel access state datafor a second preset number of times; and enabling the screen menu board card to read microphone volume data and video channel access state data from the field programmable gate array board card in a staggered manner through an interface. Thus, serial access of the interface between the screen menu board card and the field programmable gate array board card can be realized, interface access conflicts are avoided, and the real-time performance of microphone volume data and video channel access state data is ensured.

The invention relates to a method for sharing a single EDMA (Enhanced Direct Memory Access) channel by multiple cores. The method comprises the following steps: 1, distributing EDMA Channelh and hardware semaphore HwSemh to a master core, distributing EDMA Channels to slave cores, and initializing the EDMA Channelh, the hardware semaphore HwSemh and the EDMA Channels; 2, applying, by the master core and the slave cores, the EDMA Channelh via the hardware semaphore HwSemh; 3, configuring PaRAM for the master core or the slave cores getting the EDMA Channelh; 4, enabling EDMA to transmit data, and receiving an EDMA interrupt generated after the data is transmitted; and 5, after the data is transmitted, releasing the hardware semaphore HwSemh and PaRAM resources. The method has the advantages that each core can directly transmit data via the EDMA channel, inter-core forwarding is not needed and the like.

The invention discloses an aircraft power supply system communication architecture, and the architecture is characterized in that the architecture is based on a two-stage communication network of AFDXand CAN. The method has the advantages that the hardware overhead is reduced, the product complexity is reduced, the reliability is improved, and meanwhile, the size and the weight of the product arereduced.

An object is to avoid an access conflict between a plurality of devices that access an IC module.

A first device (a payment terminal installed in a store, an entrance gate of a station) and a second device (a portable terminal) can access an IC module that is used in an electronic money system. The second device has the function of receiving (detecting) waves (for example, ultrasound) having a predetermined pattern. The predetermined waves indicate that the first device is accessing the IC module. The predetermined waves may be continuously generated from the first device or may be continuously generated from another device (for example, a device installed near the first device). When the second device detects the waves having the predetermined pattern, the second device refrains from accessing the IC module. This makes it possible to implement autonomous conflict control between a plurality of devices that access the IC module that does not have an adequate conflict control function without providing a special control circuit or the like.

The invention provides a satellite load FPGA with a BRAM and a use method thereof, the satellite load FPGA comprises: an internal algorithm module, a three-mode voting module, the BRAM and a self-refreshing module; the input of the internal algorithm module is correct output data after passing through the three-mode voting module, and the internal algorithm module is used for processing configuration items of the satellite load FPGA; the three-mode voting module is used for acquiring data output by the three-mode BRAM and carrying out three-mode redundancy voting; and the BRAM and the self-refreshing module is used for storing on-orbit parameters and controlling self-refreshing of the on-orbit parameters. According to the satellite load FPGA, the self-refreshing function of the BRAM can be completed without intervention of an external processor, and the problems that a traditional BRAM anti-radiation reinforcement method consumes more resources, and the access conflict risk of the processor is caused can be solved. The problem of satellite load FPGA data errors caused by accumulation of single event upset of the BRAM is solved.

The invention provides a virtual network hard disk mounting method, a local area network server, a user terminal and a system. The method, which is applied to a local area network server, comprises the following steps: receiving a mounting request sent by a first user terminal in a local area network; judging whether the first user terminal is allowed to mount a virtual network hard disk according to the mounting request; and when the first user terminal is allowed to mount a virtual network hard disk, generating a first virtual network hard disk by mapping for the first user terminal, wherein one virtual network hard disk can be mounted only on one user terminal. Thus, the consistency of data is ensured, and user access conflict is prevented. Moreover, the virtual network hard disk is locally generated by mapping at the user terminal, namely, a complete hard disk is provided locally, so that users can operate data directly.

The invention discloses a redundant system communication method based on dual-port RAM. Aiming at the problems of slow signal data transmission speed and poor data reliability of vehicle-mounted signal equipment in the prior art, the invention proposes a multi-role-based ring buffer method, taking multiple measures to avoid access conflicts, increasing the data interaction rate of dual-port RAM, and ensuring the security and reliability of data interaction in redundant systems. Data transmission is improved, and the security of the system is also improved.

There is provided an information processing apparatus. The apparatus comprises: a processor; at least one I2C device; and a processor support chip. The processor support chip comprises a local service controller and a jointly addressable memory space and has an interface to the processor for the transfer of information therebetween. The processor support chip also has an interface for communication with a service processor; and an I2C interface for communication with the at least one I2C device. The local service controller has exclusive read and write access to the I2C interface; and is operable to maintain a data structure indicating a current value associated with the I2C device in the jointly addressable memory space for access by the processor and the service processor.

The invention relates to a method for designing a voice microprocessor, particularly, the program of the voice microprocessor directly operates on a universal serial flash memory chip; the universal serial flash memory chip can be selected in accordance with capacity based on the actual requirement; and compared with the fixed capacity of the program in the voice microprocessor, a user application program is not restricted by the capacity.