Multicore architecture supporting dynamic binary translation

A technology of dynamic binary and architecture, applied in the direction of memory system, program control design, combination of various digital computers, etc., can solve the problems of low data access delay, small cache access conflict, high translation throughput, etc.
CN102073533AInactive Publication Date: 2011-05-25NAT UNIV OF DEFENSE TECH

Patent Information

Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
NAT UNIV OF DEFENSE TECH
Publication Date
2011-05-25
Estimated Expiration
Not applicable · inactive patent

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Abstract

The invention discloses a multicore architecture supporting dynamic binary translation, aiming to solve the problems of Cache access conflict, main memory conflict and the like during dynamic binary translation. The multicore architecture comprises a plurality of processor cores, a plurality of primary Caches, a plurality of translation cache units, a secondary Cache and a main memory controller,wherein the primary Caches and the translation cache units are private for each processor core; the secondary Cache and the main memory controller are shared by all the processor cores; each translation cache unit comprises a communication control unit, a cache management unit and a data memory unit; the communication control unit comprises a multi-channel selector, a communication control unit controller, a transmission bus and three registers; the cache management unit comprises a page replacement component and a cache management control component; and the data memory unit comprises a source architecture binary code cache area, a target architecture binary code cache area and a page mapping table. The multicore architecture has the following technical effects: the data access latency isreduced, the translation throughput is high and the Cache access conflict is less.
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Description

technical field

[0001] The invention relates to a microprocessor architecture in the field of integrated circuits, in particular to a multi-core architecture supporting dynamic binary translation. Background technique

[0002] Binary Translation (Binary Translation) such as figure 1 As shown, it is used to simulate heterogeneous computer architecture, execute binary code without source program, and assist in migrating from one architecture or operating system to another architecture or operating system, which is an important way of computing system virtualization. A dynamic binary translator generally includes a translation module and an execution module. Correspondingly, the translation process is divided into a translation phase and an execution phase. In the translation stage, the translation module reads the source machine code blocks and converts them into executable binary code blocks on the target machine. In the execution phase, the execution module reads a block o...

Claims

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