32results about How to "Reduce access overhead" patented technology

A multiple protection group (MPG) erasure-resilient coding method for constructing MPG codes for encoding and decoding data. The MPG codes constructed herein protect data chunks of data in multiple protection groups and subgroups. In general, the MPG erasure-resilient codes are constructed by locating data chunks into multiple protection groups and assigning at least one parity chunk to each protection group. Basic MPG codes are constructed from existing Maximum Distance Separable (MDS) codes by splitting at least some of the parity chunks into local parities for each of the multiple protection groups and projecting local parities onto each of the groups. Generalized MPG codes have a Maximally Recoverable property that can be used to determine whether an erasure pattern is recoverable or unrecoverable. Generalized MPG codes can recover any erasure pattern that is recoverable.

An apparatus, system, and method are disclosed for deduplicating storage cache data. A storage cache partition table has at least one entry associating a specified storage address range with one or more specified storage partitions. A deduplication module creates an entry in the storage cache partition table wherein the specified storage partitions contain identical data to one another within the specified storage address range thus requiring only one copy of the identical data to be cached in a storage cache. A read module accepts a storage address within a storage partition of a storage subsystem, to locate an entry wherein the specified storage address range contains the storage address, and to determine whether the storage partition is among the one or more specified storage partitions if such an entry is found.

A method and system for allowing a processor or I / O master to address more system memory than physically exists are described. A Compressed Memory Management Unit (CMMU) may keep least recently used pages compressed, and most recently and / or frequently used pages uncompressed in physical memory. The CMMU translates system addresses into physical addresses, and may manage the compression and / or decompression of data at the physical addresses as required. The CMMU may provide data to be compressed or decompressed to a compression / decompression engine. In some embodiments, the data to be compressed or decompressed may be provided to a plurality of compression / decompression engines that may be configured to operate in parallel. The CMMU may pass the resulting physical address to the system memory controller to access the physical memory. A CMMU may be integrated in a processor, a system memory controller or elsewhere within the system.

The invention discloses a method for storing diagonal data of a sparse matrix and a SpMV realization method based on the method. The storage method comprises the following steps of: (1) scanning a sparse matrix A line by line and representing a position of a non-zero-element diagonal by using number of the diagonal; (2) segmenting the matrix A into a plurality of sparse sub-matrixes by using an intersection of the non-zero-element diagonal and the lateral side of the matrix A as a horizontal line; and (3) storing elements on the non-zero-element diagonal in each sparse matrix to a val array according to the line sequence. The SpMV realization method comprises the following steps of: (1) traversing the sparse matrixes and calculating vector multiplier y=A1*x of the sparse matrix in each sparse sub-matrix; and (2) merging the vector multipliers of all sparse sub-matrixes. The data storage method disclosed by the invention is not required to store row indexes of the non-zero elements, thereby reducing access expense and requirements on a storage space; a smaller storage space is occupied by the diagonal and the index array of the x array, so that the access complexity is reduced; andall the data required for calculation are continuously accessed, so that a complier and hardware can be optimized sufficiently.

A method, apparatus and system for processing access information of a storage device. The method comprises: a processor of an access device determines a storage device identifier corresponding to a virtual address according to the virtual address comprised in an access request initiated by a process; generates an access request message, the access request message comprising an access address; and sends, according to the storage device identifier, the access request message to the processor of the storage device that the storage device identifier points to, so that the processor of the storage device executes, according to the access address comprised in the access request message, access request operation in a storage medium that the access address points to. The access performance of an integrated storage device is improved.

The invention discloses a Hash Bloom filter and a data forwarding method for name search in NDN. The Hash Bloom filter consists of g counter Bloom filters and g counters located in the on-chip memory It consists of g hash tables located in the off-chip memory; each of the hash tables is associated with 1 counter Bloom filter and 1 counter; the hash Bloom filter is selected by the secondary hash method The complete information of the FIB / CS / PIT entries in the NDN router is uniformly distributed and stored in g counter Bloom filters and g hash tables. The HBF of the present invention utilizes the positioning and filtering functions of the CBF in the on-chip memory to greatly reduce the access overhead of the off-chip memory, thereby reducing the overall access cost of the HBF, increasing the forwarding rate of data packets, and effectively avoiding flood attacks at the same time.

The invention discloses a method for realizing multiple access with a random number statement, which mainly solves the problems of low channel utilization rate and long channel access delay caused by overmany time slots of an avoiding time period in the conventional priority-based multiple access method. The method is implemented by a process comprising a channel monitoring time period, a priority competition time period, a random number statement time period and a data transmission time period. In the channel monitoring time period, channels are monitored, and a current channel is judged whether to be idle or not. In the priority competition time period, the service priority of each station is stated, and the stations with the highest service priority are screened according to statement results. In the random number statement time period, random numbers are generated by the station with the highest service priority, and are stated, and the station with the greatest stated random number may obtain a data transmission opportunity. The method has the advantages of low channel access overhead, high channel utilization rate and short channel access delay, and can be used for Ethernet over cable (EoC) communication.

The invention relates to a data storage method and device. The method includes the following steps of obtaining newly-added data, generating corresponding time stamps for all the newly-added data, storing the corresponding data in a cache according to the reverse order of the time stamps, removing the data meeting set conditions out of the cache after the set capacity of the cache is reached, combining the removed data with data in a generated latest data file, dividing the data outside the generated latest data file according to the set capacity of the data file, generating a new data file, generating indexing information for the new data file, and renewing the indexing information of the generated latest data file. By generating the corresponding time stamps for all the data and storing the data in the cache according to the reverse order of the time stamps, the size of the data listed in this way is not limited by the maximum key value, the data can be read in the cache or the data file when read subsequently, the whole list does not need to be read, flow waste is reduced, and data access expenditures are reduced.

The embodiment of the invention provides a panoramic graph splicing method based on a virtual sampling channel model and a method for detecting a defect state of a guard railing of a high-speed railway. The detection method comprises: a forward motion video recording a high-speed railway environment state is obtained; with a panoramic graph splicing method based on a virtual sampling channel model, the forward motion video is converted into a left panoramic graph and a right panoramic graph in a railway operating environment, wherein the left panoramic graph and the right panoramic graph are used as a guard railing panoramic graph; on the basis of a maximum entropy segmentation principle, positions of a guard railing and a background in the guard railing panoramic graph are located to obtain a binary code formed by 0 and 1; run coding is carried out on th binary code; according to the run coding, a pixel width Dcur of a background area between two adjacent guard railings is calculated; and according to the pixel width Dcur of the background area between two adjacent guard railings and a normal pixel distance d between the two adjacent guard railings, whether defects exist at the two adjacent guard railings is determined.

The invention discloses a data processing method and device. The data processing method includes the flowing steps: acquiring a first preset tree structure, wherein the tree structure is used for storing a preset data object; acquiring a second preset tree structure, wherein the second preset tree structure is used for requesting a path of the data object in a target node in the first preset tree structure; extracting a sub-tree structure corresponding to the second preset tree structure from the first preset tree structure; receiving a trigger signal, wherein the trigger signal is used for processing the data object in the first preset tree structure according to the sub-tree structure; and processing the data object in the first preset tree structure by executing the trigger signal. The data processing method and device can solve the technical scheme that when a Key-Value storage database reads or writes in a part of data, all the data objects need to be processed.

Provided are a file access method and system. The method includes: a file system drive module receiving a first access request sent by an upper layer application; the file system drive module converting the first access request into a second access request suitable for accessing a key value database according to the correlation between an access interface corresponding to the upper layer application and an access interface of the key value database; the file system drive module sending the second access request to a client of the key value database; the client of the key value database searching for a corresponding file content or directory entry content or file attribute or directory entry attribute from a key value database stored at a server end of the key value database according to the second access request. As compared to the technical solution in the prior art that a POSIX file system accesses metadata layer by layer, the technical solution in the embodiments of the present invention is small in access overhead and high in access efficiency.

The invention provides a method for processing a message in a network-on-chip, and a router. The method comprises the steps that: the router receives a request message sent by a first processor core; the router determines a relationship between an address of a cached response message and an address of the request message, wherein the cached response message comprises a response message of at least one second processor core which is not directly connected to the router; and the router determines a processing manner of the request message according to the relationship. Therefore, the memory access time delay can be reduced, the overall performance of a processor can be improved, and network access overhead can be reduced by utilizing data sharing opportunities of the different processor cores.

The invention discloses a data access method, a data access device and a data access system. The method comprises the following steps that: an access request containing a block number identifier is received; a pre-established local block unit searches the corresponding relation between the block number of the local block unit and storage node resource information providing storage services according to the block number to obtain a storage node position corresponding to the block number identifier and a block data identifier; and the local block unit sends the data access request to the storage node according to the storage node position corresponding to the block number identifier and the block data identifier, wherein the storage node resource information comprises the storage node position information and the block number identifier of a storage node. By the method, the device and the system, the problem that a metadata server becomes a bottleneck of the system because the current distributed file system is required to address through the metadata server at every access is solved, and the access efficiency is low is overcome.

The invention discloses a unified bit width converting structure and method in a cache and a bus interface of a system chip. The converting structure comprises a processor core and a plurality of IP cores carrying out data interaction with the processor core through an on-chip bus, and a memorizer controller IP is communicated with an off-chip main memorizer. The processor core comprises an instruction assembly line and a hit judgment logic unit receiving an operation instruction of the instruction assembly line. An access bit width judgment unit and a bit width / address converting unit are arranged between the hit judgment logic unit and the cache bus interface, the hit judgment logic unit sends a judgment result to the instruction assembly line, and the processor core is connected with the on-chip bus through the cache bus interface. According to the converting method, for the read access of a byte or a half byte, if cache deficiency happens and the access space belongs to the cache area, the bit width / address converting unit converts the read access of the byte or the half byte into one-byte access, access and storage are finished through the bus, an original updating strategy is not affected, and flexibility can exist.