31results about How to "Reduce access overhead" patented technology

A multiple protection group (MPG) erasure-resilient coding method for constructing MPG codes for encoding and decoding data. The MPG codes constructed herein protect data chunks of data in multiple protection groups and subgroups. In general, the MPG erasure-resilient codes are constructed by locating data chunks into multiple protection groups and assigning at least one parity chunk to each protection group. Basic MPG codes are constructed from existing Maximum Distance Separable (MDS) codes by splitting at least some of the parity chunks into local parities for each of the multiple protection groups and projecting local parities onto each of the groups. Generalized MPG codes have a Maximally Recoverable property that can be used to determine whether an erasure pattern is recoverable or unrecoverable. Generalized MPG codes can recover any erasure pattern that is recoverable.

An apparatus, system, and method are disclosed for deduplicating storage cache data. A storage cache partition table has at least one entry associating a specified storage address range with one or more specified storage partitions. A deduplication module creates an entry in the storage cache partition table wherein the specified storage partitions contain identical data to one another within the specified storage address range thus requiring only one copy of the identical data to be cached in a storage cache. A read module accepts a storage address within a storage partition of a storage subsystem, to locate an entry wherein the specified storage address range contains the storage address, and to determine whether the storage partition is among the one or more specified storage partitions if such an entry is found.

To lower risks of overhead on management of an access log and of a loss of the access log due to a default and to prevent deterioration in service providing performance caused by access concentration to a specific Web server in an access relaying apparatus including a plurality of proxy servers. An access relaying apparatus has a plurality of proxy servers 23, an administration server 24 for statistic processing, and a shared disk 25 accessible from them. Each of the proxy servers outputs an access log to the shared disk, and the administration server reads the access logs from the shared disk and performs statistic processing. An access limit to a specific Web server is determined based on a result of the statistic processing, it is notified to each of the proxy servers, and a number of accesses to the Web server is controlled.

The invention discloses a unified bit width converting structure and method in a cache and a bus interface of a system chip. The converting structure comprises a processor core and a plurality of IP cores carrying out data interaction with the processor core through an on-chip bus, and a memorizer controller IP is communicated with an off-chip main memorizer. The processor core comprises an instruction assembly line and a hit judgment logic unit receiving an operation instruction of the instruction assembly line. An access bit width judgment unit and a bit width/address converting unit are arranged between the hit judgment logic unit and the cache bus interface, the hit judgment logic unit sends a judgment result to the instruction assembly line, and the processor core is connected with the on-chip bus through the cache bus interface. According to the converting method, for the read access of a byte or a half byte, if cache deficiency happens and the access space belongs to the cache area, the bit width/address converting unit converts the read access of the byte or the half byte into one-byte access, access and storage are finished through the bus, an original updating strategy is not affected, and flexibility can exist.

The invention discloses a data processing method and device. The data processing method includes the flowing steps: acquiring a first preset tree structure, wherein the tree structure is used for storing a preset data object; acquiring a second preset tree structure, wherein the second preset tree structure is used for requesting a path of the data object in a target node in the first preset tree structure; extracting a sub-tree structure corresponding to the second preset tree structure from the first preset tree structure; receiving a trigger signal, wherein the trigger signal is used for processing the data object in the first preset tree structure according to the sub-tree structure; and processing the data object in the first preset tree structure by executing the trigger signal. The data processing method and device can solve the technical scheme that when a Key-Value storage database reads or writes in a part of data, all the data objects need to be processed.

An image processor, which requires a transfer rate lower than the conventional rate, for transmitting pixel data between a DDR-DRAM and a memory, and is configured of: a decoded chrominance pixel output unit which writes pixel data into a DDR-DRAM per p×q pixel unit or per p×q pixel units, each pixel unit being made up of p lines of pixels aligned in a vertical direction and q rows of pixels aligned in a horizontal direction; and a reference chrominance pixel input unit which reads out the pixel data of the pixels from the DDR-DRAM per p×q pixel unit or p×q pixel units, in which the decoded chrominance pixel output unit has an interleaving unit that interleaves q rows of p×q pixels to be written into the DDR-DRAM, so as to generate a pixel data sequence in which the pixel data of the pixels located in q rows is multiplexed and placed in a line.

The invention provides a processing unit, a processor core, a neural network training machine and a method. The processing unit comprises a calculation unit used for executing weight gradient calculation of neural network nodes; the decompression unit decompresses the obtained compressed weight signal into a weight signal and a pruning signal, the weight signal indicates the weight of each neural network node, and the pruning signal indicates whether the weight of each neural network node is used in weight gradient calculation or not; the pruning signal is used to control whether to allow access to an operand memory storing an operand used in the weight calculation, and the pruning signal is also used to control whether to allow the calculation unit to perform a weight gradient calculation using the weight signal and the operand. According to the invention, the calculation overhead of a processor and the access overhead of a memory are reduced when the weight gradient of the neural network is determined.

The invention belongs to the technical field of Internet of Things data services, and aims to provide a centralized interface communication concurrency control system and a control method thereof. The present invention includes a user front-end module, a central processing platform, a central front-end module, and a message queue. The interface transaction mode between the central processing platform and a single point adopts a multi-thread synchronous transaction mode, and the fault and performance bottleneck of a single point are eliminated. It will affect the access of other points; the user front-end module is provided with a memory for storing user verification information, and judging whether the user who initiates the transaction has transaction authority through comparison, and performing an integrity check on the user's transaction data ; The present invention optimizes the existing interface communication mode and improves the interface transaction performance. When the central processing platform conducts transactions with multiple single points, through the multi-threaded processing control of the interface transactions, the extension of single point performance problems to the central processing platform is avoided. Dynamic allocation of single-point concurrent requests improves system performance and reduces waste of request overhead.