15results about How to "Improve memory access efficiency" patented technology

The invention provides a parallel iteration solving method and system for an electromagnetic finite element equation set, and relates to the technical field of electromagnetic finite elements, and the method comprises the steps: constructing a to-be-solved electromagnetic finite element equation set # imgabs0 #; dividing the electromagnetic finite element equation set into a plurality of calculation sub-tasks, and distributing a sub-matrix block # imgabs 1 # and a sub-right-end item vector # imgabs 2 # of the sub-tasks to each process in the super computer; by means of the initialized Hoseholder-GMRES algorithm, the processes are subjected to subtask calculation in parallel, and the local optimal solution # imgabs3 # of each process is obtained; summarizing the local optimal solution # imgabs4 # of each process to obtain an optimal solution # imgabs5 # of the electromagnetic finite element equation set; according to the method, the electromagnetic finite element, the Householder-GMRES algorithm and parallel computing are combined, and the solving efficiency of the linear equation set of the electromagnetic finite element is improved by utilizing a parallel optimization technology.

The invention relates to the technical field of Internet of Vehicles target detection, in particular to an Internet of Vehicles multi-scene target detection system and method based on an RISC-V architecture, and the method comprises the steps: S1, obtaining image data, storing the image data in a DMA cache region preset on an RISC-V hardware calculation module, and setting the DMA cache region to be of a fixed size; s2, mapping the image data in the DMA cache region to an address space of a process on an RISC-V hardware calculation module by utilizing an mmap mechanism; s3, preprocessing the image data by using an RVV instruction; s4, after target detection model parameters are loaded for the first time, caching the preprocessed image data into a heterogeneous shared memory by using a cache consistency protocol supported by an RISC-V hardware calculation module, performing model reasoning, and obtaining perception information; s5, performing post-processing on the model reasoning result through a self-defined post-processing function, and obtaining display information; and the real-time frame rate of target detection, the overall performance of the system and the memory access efficiency are improved.

The invention relates to the technical field of computers, in particular to a triangle counting implementation method and device for a graphics processor, and the method comprises the steps: obtaining graphic data of the graphics processor; recognizing neighbor lists of all the vertexes in the graphic data, constructing a hash tree without a lock according to the neighbor lists of all the vertexes, and establishing an index array of the hash tree corresponding to all the vertexes; when the vertex of the target graph is accessed, traversing all neighbor graph nodes of the vertex of the target graph in parallel, and mapping neighbor lists of all neighbor graph nodes to a continuous memory area; and realizing triangle counting based on the index array and the continuous memory region. Therefore, the problems of poor GPU computing power, computing efficiency, memory access efficiency and the like during triangle counting in related technologies are solved.

The application discloses a self-adaptive balanced division method based on GPU acceleration sparse-dense matrix multiplication, and comprises the following steps: analyzing a sparse matrix, determining long rows affecting parallel performance; dividing the long rows into equal "parts"; storing the divided sparse matrix by using a new storage format; loading all nonzero elements in the "parts" to a shared memory on a GPU; consuming the nonzero elements in the shared memory and multiplying corresponding elements of a dense matrix; adding the parts from the same row and obtaining a final result. The application aims at the current situation that long rows lead to low parallel efficiency when a row division mechanism is used in GPU acceleration sparse-dense multiplication, and proposes a self-adaptive balanced division method based on the structure characteristics of a GPU. The "parts" are used to replace rows as parallel granularity, and the size of the "parts" is controlled within a reasonable range to ensure that a thread group has enough threads to effectively parallelize the nonzero element task, and the similar size of the "parts" avoids the load imbalance among the thread groups.

The application discloses a DMA accessing method and device supporting online data reorganization, and relates to the technical field of data processing, which comprises the following steps: when a DMA engine receives a DMA transmission instruction, it is judged whether there is a data reorganization instruction in the DMA transmission instruction; if yes, the data transmission direction and data reorganization parameter information are obtained; the DMA engine analyzes and splits the received DMA instruction into an access request and sends the access request to an upstream storage in the transmission direction; when the DMA engine receives access response data sent by the upstream storage, the response data is reorganized and stored in a data buffer in the DMA engine; when the data buffer collects all data in the current DMA transmission instruction, the data is forwarded to a downstream storage in a reorganized format according to the data reorganization parameters in the DMA transmission instruction. The application supports online data reorganization, makes the data reorganization process transparent to the operation core, provides convenience and flexibility for programmers, and reduces the implementation cost and power consumption of data format conversion.

The embodiment of the invention discloses a cache partition configuration method, which comprises the following steps: obtaining grouping identifiers from structural data of a control group, mapping the grouping identifiers to partition identifiers of a cache, and enabling the grouping identifiers and the partition identifiers to be in one-to-one correspondence, and utilizing a cache partition corresponding to a pre-configured partition identifier to provide a cache function for a task corresponding to the partition identifier, wherein the task of the partition identifier is a task corresponding to the grouping identifier corresponding to the partition identifier. The embodiment of the invention further provides a cache partition configuration device and computer equipment.

The invention discloses a server-free remote memory access performance optimization method based on cross-process memory tracking, and belongs to the technical field of computer memory management. The method comprises the following steps: designing a memory state table as a unified perception layer for remote memory access of homologous server-free containers, and realizing cross-process tracking of memory page states among different containers; a memory state table query process is embedded into hardware page table traversal, page state query is completed by hardware acceleration, and extra overhead on a memory access key path is eliminated; the remote memory access is merged and optimized based on the memory state table, cached local memory pages are reused in the container creation stage, the same remote memory access requests are merged in the operation stage, and the page missing exception frequency and the network bandwidth contention are reduced. According to the method, extra overhead caused by remote memory access in a server-free environment is effectively reduced, page missing abnormity and network bandwidth contention in a concurrent scene are greatly reduced, and the running performance and the system expandability of memory-intensive server-free applications are remarkably improved.

The present application provides a smart network card HMU storage method, system, medium, program product and terminal based on large page memory. First, when the smart network card driver is initialized, the system's available large page memory support is checked. If supported, a continuous physical memory block is applied for the network card PCIe DMA from the large page memory area at one time. If the large page memory is not supported, the HMU memory is still applied from the system's ordinary memory page. The present application improves memory access efficiency, reduces management costs, optimizes system performance, saves resources, reduces host pressure, and increases flexibility. At the same time, it simplifies the memory management process and solves the problem that the existing HMU memory management method cannot effectively cope with the Linux system's default small memory pages and memory swap mechanism, resulting in low memory utilization efficiency and affecting network card performance.

The application relates to a data access method, device, equipment and storage medium. The application is applied to the field of data processing. The method comprises the following steps: determining a cyclic offset and a shift direction for performing a shift operation on to-be-processed data; the to-be-processed data is an ordered set data; in the shift direction, the to-be-processed data is read in a mode of reading multiple sequence data each time; based on the cyclic offset and the shift direction, the coordinates of the to-be-processed data after the shift are calculated, the multiple sequence data read are stored according to the coordinates after the shift, and the data corresponding to the to-be-processed data after the shift is obtained. The method can process multiple rows and multiple columns of data blocks at a time, thereby improving the data access efficiency.

The invention provides a time sequence control method and circuit for FPGA BRAM read-write conflict, and the method comprises the steps: employing two time sequence circuits for generating a working time sequence during the read-write conflict, enabling an initial clock to act on a first time sequence circuit, enabling the first time sequence circuit to generate a read operation time sequence, and enabling the initial clock to act on a second time sequence circuit after the read operation of the first time sequence circuit is completed; and controlling the second time sequence circuit to generate a write operation time sequence, thereby achieving the purpose of controlling read-write by using one time sequence path, avoiding competition caused by read-write conflicts, and improving the memory access efficiency of the BRAM.

The invention relates to a memory access method and device, computer equipment, a computer readable storage medium and a computer program product, and can be applied to the technical field of computers. The method comprises the following steps: sending a first memory access request to a response end; the first memory access request carries a request serial number; receiving a first memory access response which is returned by the response end based on the first memory access request and corresponds to the request serial number; the first memory access response carries a response serial number; determining a missing serial number of the first memory access request according to the request serial number and the response serial number; sending a second memory access request carrying the missing serial number to the response end; the second memory access request is used for indicating the response end to return a second memory access response corresponding to the missing serial number. By adopting the method, the memory access efficiency can be improved.

The application relates to the technical field of artificial intelligence, and provides a data processing method, a host, equipment, a system and a storage medium, which comprise the following steps: acquiring a mapping relationship from source data elements to target data elements and feature weight information; constructing a sparse index based on the mapping relationship and the feature weight information; and sending the sparse index to a computing device, so that the computing device reads the numerical values of each source data element corresponding to the target data elements based on the sparse index and performs accumulated writing. According to the application, the sparse index is pre-constructed based on the data mapping relationship at the host end, and the computing device is guided to perform non-competitive reading and accumulated writing according to the sparse index, so that the dense scattering writing operation prone to conflict is converted into the regular concentrated reading operation without competition, the atomic writing bottleneck of the computing device is bypassed, and the memory access efficiency and the comprehensive processing performance of the heterogeneous computing system are greatly improved.

The application provides a Cache write cache device and a control method thereof, and relates to the technical field of artificial intelligence chips. The device comprises: a write cache table for storing a plurality of write cache entries, each write cache entry corresponding to attribute information of a Cache line; a memory for storing data of the Cache line corresponding to each write cache entry; a write cache control unit for processing storage requests and loading requests based on the write cache table, and for writing the data of the Cache line corresponding to the write cache entry from the memory to a data storage unit when a preset write-back condition is met; a loading request queue for buffering loading request information from a previous execution unit or a previous Cache; and an effective address generation module for generating a corresponding effective write-back address according to a write data effective flag signal recorded in the write cache entry when performing a write-back operation. The application effectively reduces the write-back pressure on the lower-level storage, eliminates the structural blockage of the storage backend to the computing frontend, and significantly improves the overall memory access efficiency and computing throughput.

The present invention provides a parallel iterative solution method and system for electromagnetic finite element equations, which relates to the field of electromagnetic finite element technology, including: constructing an electromagnetic finite element equation to be solved; dividing the electromagnetic finite element equation into a plurality of computing subtasks, and allocating the sub-matrix blocks and sub-right-hand-end term vectors of the subtasks to each process in a supercomputer; using the initialized Householder‑GMRES algorithm, each process performs the subtask calculation in parallel to obtain a local optimal solution of each process; summarizing the local optimal solutions of each process to obtain the optimal solution of the electromagnetic finite element equations; the present invention combines electromagnetic finite elements, the Householder‑GMRES algorithm, and parallel computing, and uses parallel optimization technology to improve the efficiency of solving electromagnetic finite element linear equations.

Embodiments of the present disclosure provide a data processing method, apparatus, device, and computer-readable storage medium. The method provided by the embodiments of the present disclosure optimizes the performance of the back propagation calculation of the depth-separable two-dimensional convolution operator, by pre-loading part of the data of the output tensor from the off-chip memory into the group shared memory each time, and pre-loading the data of the weight matrix from the off-chip memory into the thread private register, so as to use the data of the output tensor loaded into the group shared memory and the data of the weight matrix to calculate the corresponding data in the input tensor, thereby obtaining the input tensor through back propagation based on the output tensor and the weight matrix, wherein the high memory access bandwidth of the group shared memory is used to cache data, which can improve the memory access efficiency of the data and improve the performance of the back propagation calculation of the depth-separable two-dimensional convolution operator.