6results about How to "Improve memory access efficiency" patented technology

The application discloses a self-adaptive balanced division method based on GPU acceleration sparse-dense matrix multiplication, and comprises the following steps: analyzing a sparse matrix, determining long rows affecting parallel performance; dividing the long rows into equal "parts"; storing the divided sparse matrix by using a new storage format; loading all nonzero elements in the "parts" to a shared memory on a GPU; consuming the nonzero elements in the shared memory and multiplying corresponding elements of a dense matrix; adding the parts from the same row and obtaining a final result. The application aims at the current situation that long rows lead to low parallel efficiency when a row division mechanism is used in GPU acceleration sparse-dense multiplication, and proposes a self-adaptive balanced division method based on the structure characteristics of a GPU. The "parts" are used to replace rows as parallel granularity, and the size of the "parts" is controlled within a reasonable range to ensure that a thread group has enough threads to effectively parallelize the nonzero element task, and the similar size of the "parts" avoids the load imbalance among the thread groups.

The application discloses a DMA accessing method and device supporting online data reorganization, and relates to the technical field of data processing, which comprises the following steps: when a DMA engine receives a DMA transmission instruction, it is judged whether there is a data reorganization instruction in the DMA transmission instruction; if yes, the data transmission direction and data reorganization parameter information are obtained; the DMA engine analyzes and splits the received DMA instruction into an access request and sends the access request to an upstream storage in the transmission direction; when the DMA engine receives access response data sent by the upstream storage, the response data is reorganized and stored in a data buffer in the DMA engine; when the data buffer collects all data in the current DMA transmission instruction, the data is forwarded to a downstream storage in a reorganized format according to the data reorganization parameters in the DMA transmission instruction. The application supports online data reorganization, makes the data reorganization process transparent to the operation core, provides convenience and flexibility for programmers, and reduces the implementation cost and power consumption of data format conversion.

The invention discloses a server-free remote memory access performance optimization method based on cross-process memory tracking, and belongs to the technical field of computer memory management. The method comprises the following steps: designing a memory state table as a unified perception layer for remote memory access of homologous server-free containers, and realizing cross-process tracking of memory page states among different containers; a memory state table query process is embedded into hardware page table traversal, page state query is completed by hardware acceleration, and extra overhead on a memory access key path is eliminated; the remote memory access is merged and optimized based on the memory state table, cached local memory pages are reused in the container creation stage, the same remote memory access requests are merged in the operation stage, and the page missing exception frequency and the network bandwidth contention are reduced. According to the method, extra overhead caused by remote memory access in a server-free environment is effectively reduced, page missing abnormity and network bandwidth contention in a concurrent scene are greatly reduced, and the running performance and the system expandability of memory-intensive server-free applications are remarkably improved.

The application relates to a data access method, device, equipment and storage medium. The application is applied to the field of data processing. The method comprises the following steps: determining a cyclic offset and a shift direction for performing a shift operation on to-be-processed data; the to-be-processed data is an ordered set data; in the shift direction, the to-be-processed data is read in a mode of reading multiple sequence data each time; based on the cyclic offset and the shift direction, the coordinates of the to-be-processed data after the shift are calculated, the multiple sequence data read are stored according to the coordinates after the shift, and the data corresponding to the to-be-processed data after the shift is obtained. The method can process multiple rows and multiple columns of data blocks at a time, thereby improving the data access efficiency.

The application relates to the technical field of artificial intelligence, and provides a data processing method, a host, equipment, a system and a storage medium, which comprise the following steps: acquiring a mapping relationship from source data elements to target data elements and feature weight information; constructing a sparse index based on the mapping relationship and the feature weight information; and sending the sparse index to a computing device, so that the computing device reads the numerical values of each source data element corresponding to the target data elements based on the sparse index and performs accumulated writing. According to the application, the sparse index is pre-constructed based on the data mapping relationship at the host end, and the computing device is guided to perform non-competitive reading and accumulated writing according to the sparse index, so that the dense scattering writing operation prone to conflict is converted into the regular concentrated reading operation without competition, the atomic writing bottleneck of the computing device is bypassed, and the memory access efficiency and the comprehensive processing performance of the heterogeneous computing system are greatly improved.

The application provides a Cache write cache device and a control method thereof, and relates to the technical field of artificial intelligence chips. The device comprises: a write cache table for storing a plurality of write cache entries, each write cache entry corresponding to attribute information of a Cache line; a memory for storing data of the Cache line corresponding to each write cache entry; a write cache control unit for processing storage requests and loading requests based on the write cache table, and for writing the data of the Cache line corresponding to the write cache entry from the memory to a data storage unit when a preset write-back condition is met; a loading request queue for buffering loading request information from a previous execution unit or a previous Cache; and an effective address generation module for generating a corresponding effective write-back address according to a write data effective flag signal recorded in the write cache entry when performing a write-back operation. The application effectively reduces the write-back pressure on the lower-level storage, eliminates the structural blockage of the storage backend to the computing frontend, and significantly improves the overall memory access efficiency and computing throughput.