Video decoder of dual-buffer-memory structure and control method

A video decoder and memory technology, applied in the field of video decoding, can solve the problems of chip area expansion, memory inconsistency, and high manufacturing costs, and achieve the effect of improving memory access efficiency and reducing bandwidth requirements

Inactive Publication Date: 2014-07-30
CHINA AGRI UNIV
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Problems solved by technology

[0007] There are many standards for video decoding: H.264, MPEG2 / MPEG4, VP8, AVS, RV, VC1, etc. Although the composition and structure of different decoding standards are roughly the same, the memory required by the functional modules corresponding to different video standards is very inconsistent. As a result, multi-standard decoders require a large number of scattered memories with different depths and widths. The large number and scattered memories lead to a large increase in chip area and high manufacturing costs.

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[0033] In order to describe the technical solution of the present invention more clearly, the present invention will be described in detail below in conjunction with the drawings and specific embodiments.

[0034] like figure 2 As shown, the video decoder of the present invention is connected with the main controller of the system. The video decoder includes memory access control registers, main memory interface, auxiliary storage interface, bus matrix, main memory, auxiliary memory and decoder. The memory access control register is connected with the main controller and the decoder, and the main controller configures the hardware function module of the decoder through the memory access control register whether to use the auxiliary memory to save intermediate data and the corresponding memory access address space. The decoder is connected with the memory access control register, the main memory interface, and the auxiliary memory interface. After receiving the decoding start...

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Abstract

The invention provides a video decoder of a dual-buffer-memory structure. The video decoder comprises a storage access control register, a main storage interface, an auxiliary storage interface, a bus matrix, a main storage, an auxiliary storage and an encoder body. According to the format of input and compressed video streams, a main controller configures the storages used by hardware functional modules of the decoder body through the storage access control register, and sets corresponding access and storage addresses and spaces. After the decoder body receives a decoding start command sent by the main controller, the hardware functional modules in the decoder body are started and carry out concurrent execution, and an access and storage request is sent to the main storage interface or the auxiliary storage interface according to setting of a storage access controller. The main storage interface and the auxiliary storage interface receive the access and storage request of the hardware functional modules of the decoder body and have access to the corresponding storage after arbitration. According to a method and a circuit, a storage centralized management mode is adopted, different storage access modes are configured to the hardware functional modules of the decoder body according to the video streams of a multi-standard compressed encoding format, the areas of the storages are saved, and bandwidth requirements of a system are effectively reduced.

Description

Technical field: [0001] The invention relates to the field of video decoding, in particular to a video decoder with a double-buffer memory structure related to multi-standard video streams and a data storage and control method. Background technique: [0002] In the field of video decoding, video decoding motion compensation, intra prediction, deblocking filtering, etc. require a large number of row and column data buffers, figure 1 Taking H.264 video decoding intra-frame prediction as an example, there are nine H.264 intra-frame prediction 4×4 luma prediction modes, including vertical prediction, horizontal prediction, DC prediction, left-bottom diagonal prediction, right-bottom diagonal prediction, vertical Lower right corner prediction, horizontal lower diagonal prediction, vertical lower left corner prediction and horizontal upper diagonal prediction, etc., determine the brightness prediction mode of the current 4x4 block according to the prediction mode of the left adjac...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H04N19/51H04N19/86H04N19/15
Inventor 薛一鸣刘晓莉姚晓明
Owner CHINA AGRI UNIV
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