47results about How to "Reduce access conflicts" patented technology

The invention discloses a shared data caching device for a plurality of coarse-grained dynamic reconfigurable arrays and a control method of the shared data caching device. The shared data caching device comprises a reconfigurable array data caching control unit, a reconfigurable array data caching unit, an external memory data prefetching caching unit and a data memory access reconfiguration unit, wherein the reconfigurable array data caching control unit is used for controlling data interaction between the reconfigurable arrays and the reconfigurable array data caching unit and data interaction between the reconfigurable array data caching unit and an external memory, the reconfigurable array data caching unit is used for storing data fetched from the external memory, the external memory data prefetching caching unit is used for prefetching data to be accessed to the reconfigurable array data caching unit, and the data memory access reconfiguration unit is used for sending address information and step length information needed by the reconfigurable array data caching unit. The control method is used for achieving data sharing between the coarse-grained dynamic reconfigurable arrays in a reconfigurable system. By means of the shared data caching device and the control method, access conflict is reduced, data processing time of the reconfigurable system is shortened, and the calculation performance of large-scale coarse-grained reconfigurable arrays is improved.

A cache memory system includes: a plurality of cache lines, each including a data section for storing data of main memory and a line classification section for storing identification information that indicates whether the data stored in the data section is for instruction processing or for data processing; a cache hit determination section for determining whether or not there is a cache hit by using the identification information stored in each of the cache lines; and a cache update section for updating one of the cache lines that has to be updated, according to result of the determination.

The invention discloses a controller for realizing configuration information cache update in a reconfigurable system. The controller comprises a configuration information cache unit, an off-chip memory interface module and a cache control unit, wherein the configuration information cache unit is used for caching configuration information which can be used by a certain reconfigurable array or some reconfigurable arrays within a period of time, the off-chip memory interface module is used for reading the configuration information from an external memory and transmitting the configuration information to the configuration information cache unit, and the cache control unit is used for controlling the reconfiguration process of the reconfigurable arrays. The reconfiguration process includes: mapping subtasks in an algorithm application to a certain reconfigurable array; setting a priority strategy of the configuration information cache unit; replacing the configuration information in the configuration information cache unit according to an LRU_FRQ replacement strategy. The invention further provides a method for realizing configuration information cache update in the reconfigurable system. Cache is updated by the aid of the LRU_FRQ replacement strategy, a traditional mode of updating the configuration information cache is changed, and the dynamic reconfiguration efficiency of the reconfigurable system is improved.

The invention discloses a parallel breadth-first search method based on a shared memory system structure. The method comprises: a worker thread grouping and binding process, a data interval partition process, and a task execution process. The method specifically comprises: obtaining a CPU topological structure of an operating environment, partitioning and binding a worker thread group; partitioning data intervals, and making the data intervals corresponding to the worker thread groups; task execution using a hierarchical ergodic method, in an execution process, automatically selecting a proper state from a series top-down state, a parallel top-down state, and a bottom-up state, as a self execution state, and when count in an activated state in a certain layer is zero, ending task execution. The method reduces communication among CPU sockets through task partition, data consistency maintenance among the CPU sockets is eliminated, and improves data reading efficiency through data binding and automatic switching, so as to improve operation efficiency of program.

The invention discloses a high-efficiency passing method for a road intersection adopting non-circular roundabout. A left turning passage for communicating two-way lanes of a major trunk road is built in the middle section of a straight through isolating band of the two-way lanes of the major trunk road; an approximately quincuncial or oval traffic ring island is formed on the intersection; resources of middle section of the road are thoroughly used for enhancing the passing capability of the intersection; and waste road resources are better applied. Under the condition that no overpass is built on a suburban intersection and a T-junction and buildings along streets are not removed, a left turning vehicle stream and a straight vehicle stream on the major trunk road quickly can pass the intersection without any parking; under the condition that the left turning vehicle stream and the straight vehicle stream on the major trunk road are not disturbed, a left turning vehicle stream and a straight vehicle stream on a secondary trunk road can successfully pass the intersection so that the passing vehicle streams on the intersection are simple and sequential; and 50% traffic light conversion is reduced, therefore, the purposes of largely enhancing the vehicle passing efficiency and realizing quick passing are achieved.

The invention discloses a method and device for preventing access collision of multiple user terminals. The method comprises the following steps: a specific user ID is allocated for each user terminal working in a time division mode in advance; when multiple user terminals working in a time division mode are activated at the same time and access a network, each user terminal determines a corresponding network access time slot according to the allocated user ID so that the user terminals activated at the same time forms an access queue for accessing the network; and each user terminal in the access queue accesses the network in sequence according to the determined time slot and sends data frames. The method has the advantages of largely reducing access collision and improving the use rate of channels when multiple user terminals are activated at the same time and need network access.

Disclosed is a cache structure for use in implementing reconfigurable system configuration information storage, comprising: layered configuration information cache units: for use in caching configuration information that may be used by a certain or several reconfigurable arrays within a period of time; an off-chip memory interface module: for use in establishing communication; a configuration anagement unit: for use in managing a reconfiguration process of the reconfigurable arrays, in mapping each subtask in an algorithm application to a certain reconfigurable array, thus the reconfigurable array will, on the basis of the mapped subtask, load the corresponding configuration information to complete a function reconfiguration for the reconfigurable array. This increases the utilization efficiency of configuration information caches. Also provided is a method for managing the reconfigurable system configuration information caches, employing a mixed priority cache update method, and changing a mode for managing the configuration information caches in a conventional reconfigurable system, thus increasing the dynamic reconfiguration efficiency in a complex reconfigurable system.

The present invention provides a source node device and a destination node in a data processing system, a data processing system, and a decoding method. The source node device includes: an encoding unit, configured to conduct an encoding processing on collected original data according to a codebook including an encoded numerical value and a sending interval corresponding to the original data so as to encode the original data into encoded data having a corresponding encoded numerical value included in the codebook, and to determine a sending interval corresponding to the encoded data included in the codebook. According to the present invention, sending intervals of different encoded data are determined and distinguished based on sending intervals corresponding to the encoded data included in the codebook, which provides a better performance on channel load, channel access collisions, energy efficiency, consumed resources or lifetime of the data processing system.

The invention provides a distributing method of uplink synchronized code, which includes setting reference for redistributing, initially configuring uplink synchronized code (SYNC_UL) for high speed uplink packet access (HSUPA) service, then redistributing SYNC_UL by radio network controller for HSUPA service according to the set reference for redistributing. The invention can improve rationality of uplink synchronized code's distribution, reduce access collision caused by unreasonable distribution of SYNC_UL, improve access performance of the system, and bring good feeling to the user in the same time.

The present invention discloses a random access method of time division synchronous code division multiple access system which is based on the distributed antennae; the method comprises the following processing that every antenna unit of the base station of the time division synchronous code division multiple access system implements the relevant operations on received random access signal and uplink synchronous code to obtain the corresponding result sequence; the relevant result sequence obtained by every antenna unit is processed to judge whether the user device which uses the uplink synchronous code for uplink access exists on every antenna unit; with the judging result, people decide whether to arrange a downlink forward-link physical access channel for the uplink synchronous code. With the technical proposal, at least two of the following beneficial effects are realized that the probability of system access conflict is reduced and the success rate of system access is increased.

The invention discloses a hybrid branch prediction device and method for out-of-order high-performance cores, and relates to the field of computer branch prediction. The device can evaluate the performance of the micro-architecture level of the processor, and reduce out-of-order high-performance processor renaming blockage caused by branch prediction failure and instruction missing; and the deviceprovides a hybrid branch predictor which is high in precision and flexible and configurable in parameterization. The hybrid branch predictor is composed of a global historical information branch TAGEpredictor, a statistical correction predictor and a cycle predictor. According to the TAGE predictor, a parameterized Tagged component and a split reading improvement strategy are utilized, high-precision branch prediction is achieved, and access conflicts are reduced; the statistical correction predictor is used for confirming or restoring the prediction result of the TAGE predictor according tothe prediction result and the confidence coefficient of the TAGE predictor; and the loop predictor is configured to predict a regular loop having a long loop subject using a replacement strategy anda loop branch conversion technique. Limited hardware storage overhead is fully utilized, access conflicts are reduced to a great extent, and the overall performance of the processor is improved whilebranch prediction precision is improved.

The embodiment of the invention provides a multi-user random access method and system utilizing angle domain cluster sparse characteristics, and a base station. The method comprises the following steps: 1, a base station side receives a signal Q sent to a base station when equipment of a user side gets access; 2, the base station side processes the received signals, wherein the step 2 specificallycomprises: performing Fourier transform Y = QW = AHW + ZW = AX + N on a received signal Q so as to convert a system model to a multi-antenna virtual angle domain, wherein the matrix W represents a discrete Fourier transform matrix, X = HW is a channel information matrix of an angle domain, n=ZW; and 3, the base station side performs pilot frequency detection and conflict resolution according to the processed signals.

The invention relates to a storage component and an artificial intelligence processor. The storage component is applied to computing cores of the artificial intelligence processor, the artificial intelligence processor comprises a plurality of computing cores, each computing core comprises a processing component and a storage component, and the storage component comprises a first storage unit, a second storage unit and a third storage unit; and the processing component includes an axon unit, a cell unit, and a routing unit. According to the storage component provided by the embodiment of the invention, the processing component and the storage component can be arranged in the computing core, so that the storage component directly receives the read-write access of the processing component, and the storage component outside the core does not need to be read and written. The distributed storage architecture of the plurality of storage units can store different data respectively, so that the processing component can access the plurality of storage units conveniently, and the distributed storage architecture is suitable for the processing component of a many-core architecture. The size of the artificial intelligence processor can be reduced, the power consumption of the artificial intelligence processor is reduced, and the processing efficiency of the artificial intelligence processor is improved.

The invention relates to a large-scale terminal random access method based on conflict estimation, which solves the problem of multi-user overload access under limited preamble resources, is suitable for the scene of burst transmission of scattered small data packets of a large number of machine type devices, and specifically comprises the following steps of: firstly, performing random access; a large-scale random access protocol with low signaling overhead and controllable user conflicts is designed; then, a multi-preamble combination random access competition scheme is provided; and finally, designing an efficient channel resource allocation scheme based on conflict estimation. According to the invention, on the premise that the number of orthogonal preambles is not increased, large-scale terminal random access conflicts are reduced, the access success probability of users is improved, and the multiple access capability of a cellular network is improved.