A hybrid branch prediction device and method for out-of-order high-performance cores

Abstract

The invention discloses a hybrid branch prediction device and method of out-of-order high-performance cores, and relates to the field of computer branch prediction. The device can perform performance evaluation at the microarchitecture level of the processor, and alleviate the renaming blockage of out-of-order high-performance processors caused by branch prediction failures and missing instructions; the device provides a high-precision, flexible and configurable hybrid The branch predictor is composed of a global historical information branch TAGE predictor, a statistical correction predictor and a cycle predictor; the TAGE predictor utilizes parameterized Tagged components and split read improvement strategies to achieve high-precision branch prediction and reduce access conflict; the statistical correction predictor is used to confirm or restore the prediction result of the TAGE predictor according to the prediction result and confidence of the TAGE predictor; the cycle predictor is used to use the replacement strategy and the cycle branch reduction technology to predict The principal's rule loop. The invention makes full use of limited hardware storage overhead, greatly reduces access conflicts, and improves the overall performance of the processor while improving branch prediction accuracy.

Description

technical field [0001] Embodiments of the present invention relate to the field of branch prediction, and in particular to a hybrid branch prediction device and method for out-of-order high-performance cores. Background technique [0002] With the continuous improvement of the performance of the processor core, the processor micro-architecture is also increasingly complex. Faced with increasingly complex processor microarchitecture and limited development time, how to effectively evaluate processor performance has become an important problem to be overcome in processor design. The increase in the number of transistors on a single chip allows the processor to adopt a more complex micro-architecture, and technologies such as superscalar, branch prediction, out-of-order execution, and forward-looking execution are also widely used. However, the problem brought about by the increasingly complex micro-architecture is how to conduct more effective performance analysis in the proc...

AI Technical Summary

Problems solved by technology

[0005] The purpose of the embodiments of the present invention is to provide a hybrid branch prediction device and method for out-of-order high-performance cores, to provide a high-precision hybrid branch predictor, and to solve the problem of low precision in performance analysis of existing processor cores

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