868 results about "Reading (computer)" patented technology

The invention provides a server voltage monitoring system and method, electronic equipment and a storage medium, and relates to the technical field of computers, the system comprises a complex programmable logic device CPLD, and an initial timing module, a voltage acquisition module, an abnormal data storage module, a CPU processor and a baseboard management controller BMC module which are respectively in communication connection with the CPLD. The initial timing module activates the monitoring function of the CPLD through a startup signal; the voltage acquisition module acquires voltage data under the control of the CPLD so as to read the voltage data of the server mainboard; the CPLD obtains voltage data, compares the voltage data with a reference voltage range of the abnormal data storage module, triggers an interrupt signal after identifying abnormal fluctuation voltage, and feeds back the interrupt signal to the CPU and the BMC, so that the CPU and the BMC quickly output an alarm. The system covers full-cycle monitoring from startup to BMC startup, supports efficient acquisition, dynamic detection and low-delay response of multi-path voltage, relieves the voltage pressure of a BMC monitoring mainboard, and provides reliable guarantee for power supply safety of a server.

The invention relates to a data processing method and system of an NAND FLASH storage array, computer equipment and a storage medium. The method comprises the following steps: receiving a data writing or reading instruction; and analyzing the instruction through the system-on-chip, and distributing the data to a target module in the plurality of NAND FLASH modules connected in parallel according to a preset strategy. And writing the data into the target module or reading the data from the target module through the control and communication line. And executing data management operation through the system-on-chip, specifically, writing data into different NAND FLASH modules in a dispersed manner by adopting a dynamic wear leveling algorithm so as to balance the erasing times of each module. And detecting and marking bad blocks in the NAND FLASH module in real time, and avoiding the bad blocks in calling operation after data storage. By the adoption of the method, the storage performance, reliability and expandability of satellite-borne storage can be comprehensively improved, and the method is suitable for task scenes with high reliability requirements.

The invention relates to the technical field of data processing, and provides a BMC fault recording method and device, computer equipment and a storage medium, and the method comprises the steps: responding to a kernel fault of a target operating system of a target BMC, and printing fault log information; obtaining a pre-configured memory technology device partition; transmitting the fault log information to an annular fault cache region to form cache log data; storing the cached log data in a memory technical equipment partition, and generating a fault log file; and in response to a user reading instruction, reading and outputting the fault log file of the memory technical equipment partition. According to the technical scheme provided by one or more embodiments of the invention, the fault log can be effectively recorded, maintenance personnel can timely and accurately know the fault position and the fault reason, and BMC fault diagnosis and repair can be efficiently completed.

Disclosed in the embodiments of the present disclosure are a data reading method for a chip, and a chip, a computer device, a storage medium and a computer program product. The method comprises: acquiring a data reading instruction, wherein the data reading instruction is used for instructing data reading to be performed according to reading information and data prefetching to be performed according to prefetching information; on the basis of the data reading instruction, acquiring a first data reading request, wherein the first data reading request includes the reading information and the prefetching information; sending the first data reading request to a cache module, so that in response to the first data reading request, the cache module reads and returns first target data according to the reading information, and pre-fetches and caches second target data according to the prefetching information; and receiving the first target data returned by the cache module. The embodiments of the present disclosure can reduce data request pressure between a request source and a cache module, compress a request bandwidth, improve the performance of a processor, and facilitate flexible control over a prefetching mode on a per-task basis, thereby better satisfying data reading requirements of tasks.

The invention discloses a memory fault processing method and device, electronic equipment and a readable storage medium, and relates to the technical field of computers.The method comprises the steps that when a memory line fault exists in a memory of a target system, an isolation operation is triggered for a target physical address, the target physical address at least comprises the physical address of the fault line with the memory line fault in the memory, the technical problem of system downtime caused by the fact that the memory line fault cannot be rapidly processed in the related technology is solved, the isolation process is started for the target physical address in time when the memory line fault is detected, and the system downtime is reduced. Performance reduction and data error accumulation caused by the fact that the fault line continues to participate in data reading and writing are avoided, and then the technical effect of reducing the risk of system downtime is achieved.

Embodiments of the present invention provide a storage die, a data processing method, and a computer system. The storage die includes a die interconnection interface, a computing module, and a storage module. The die interconnection interface is configured to receive a data processing command sent to the storage die and pass the data processing command to the computing module. The computing module is configured to read target data from the storage module based on the data processing command, perform an operation on the target data based on the data processing command to obtain an operation result, and store the operation result in the storage module based on the data processing command. The storage module is configured to store data. The technical solution provided by the embodiments of the present invention realizes data reading, operation, and storage of operation results inside the storage die by setting a computing module inside the storage die, avoiding the realization of both data reading and storage by the die interconnection interface of the storage die, so that the bandwidth pressure and power consumption of the die interconnection interface of the storage die can be reduced.

The invention provides a pointer type instrument automatic reading and verification method based on deep learning, and relates to the technical field of computer vision, and the method comprises the steps: 1, obtaining various types of pointer type instrument images; 2, performing data enhancement on the images in the training set; step 3, performing dial target detection and image segmentation on the instrument image; 4, performing tilt correction on the pointer type instrument picture in combination with an image segmentation result; 5, key point detection is carried out on the instrument image; 6, performing reading calculation by using an angle method to obtain the reading of the instrument; and step 7, obtaining the reading of the standard digital meter in the verification process. According to the invention, the precision of instrument dial detection in a complex environment is improved through a deep learning technology, and manual intervention is reduced; and meanwhile, the automation level and the intelligence level of instrument reading and verification are improved, higher detection efficiency and standardization are achieved, and wide application value is achieved.

The invention provides a data processing method and device of a storage device, a medium and computer equipment. The data processing method comprises the following steps: analyzing a reading request initiated by a user, and obtaining a logical addresses to be read; determining c L2P mapping tables associated with the a logical addresses according to the range of the a logical addresses, wherein c is a positive integer greater than or equal to 1; backing up an original mapping relation of the c L2P mapping tables; b latest mapping relations of a temporary information layer are updated to the c L2P mapping tables, and the original mapping relations of the c L2P mapping tables are covered; querying the updated c L2P mapping tables according to the reading request, obtaining physical addresses corresponding to the a logical addresses, and reading data; and after the reading is completed, restoring the backed-up original mapping relation to the c L2P mapping tables. Through the mapping management process of the scheme, redundancy check can be avoided, accurate locking of an updating range is realized, the check times are greatly reduced, physical limitation of bandwidth is released, and delay is greatly reduced.

The invention provides a method and a device for adjusting read voltage by recording programming positions, computer equipment and a storage medium. The method comprises the following steps of: constructing a nearest programming position table according to a nearest programming page number of an unprogrammed block, and pre-constructing a distance-state conversion table and a state-voltage conversion table; receiving a host read command, and judging the position information of a target block in the nearest programming position table; calculating and converting the position information through the distance-state conversion table and the state-voltage conversion table to obtain a read voltage; and performing a read operation based on the read voltage. According to the invention, the problems of high bit error rate of unprogrammed blocks and waste of power consumption caused by a fixed voltage strategy in a traditional storage system are solved.

The invention provides a request response method and device, equipment, a medium and a product, can be applied to the technical field of big data and the technical field of computers, and comprises the following steps: in response to a received data reading request, determining a target node set according to node states of a plurality of reading nodes in a server cluster and priorities of the reading nodes, the priority is determined according to a matching relationship between a request address of the data reading request and an operation address of each sub-cluster in the server cluster; according to the weight of each read node in the target node set, multiple accumulative weight intervals are determined, and the weights are obtained based on hardware configuration and performance data evaluation of the read nodes; matching a random value generated in the cumulative weight interval with each cumulative weight interval to determine a target weight interval corresponding to the random value; and executing a data reading operation by using a reading node corresponding to the target weight interval in the target node set.

The invention discloses a multi-person online map access method and device, a computer storage medium and equipment, and the method comprises the steps: responding to a write-in request of a client, storing to-be-stored map data in a first storage area and a second storage area, and achieving the double-layer storage of the to-be-stored map data, quick storage of the to-be-stored map data can be ensured, and the map data can be ensured not to be lost through the second storage area; in response to a reading request of a client, obtaining position coordinates in the reading request; coding based on the position coordinates to obtain routing keys corresponding to the position coordinates; reading target map data corresponding to the routing key from the first storage area or the second storage area; therefore, the real-time access of the map data can be ensured during large-scale multi-person online, and the required storage cost is lower.

The invention discloses an automatic calibration method based on deep learning multimeter reading identification and application thereof, and the method comprises the steps: obtaining calibration information, and transmitting the calibration information to a server; in response to the calibration request, sending a starting instruction to a server; acquiring a multimeter image in real time, extracting a real-time indicating value from the multimeter image based on a neural network model, and sending the real-time indicating value to an upper computer; the neural network model comprises a backbone network, a neck network and a head network, the backbone network comprises a low illumination enhancement module, a down-sampling layer and a fast spatial pyramid pooling layer, the down-sampling layer comprises alternative standard convolution modules and C2fGhostV2 modules, the C2fGhostV2 modules, and the fast spatial pyramid pooling layer is connected to the neck network through a simAM module. According to the method, the calculation amount and the parameter amount are effectively reduced, the calculation efficiency is improved, the robustness to a complex background is enhanced, full-process automation is realized, and the calibration efficiency, precision and stability are improved.

The invention discloses a data access control method and device, a storage medium and electronic equipment, and relates to the field of computers.The data access control method comprises the steps that a target reading request is received, and the target reading request is used for requesting to read data corresponding to target time from a storage space in a memory according to target address information; in response to the target reading request, positioning a target cache region corresponding to the target address information in a cache space in a memory; and extracting the target data of the target snapshot version corresponding to the target time from the reference snapshot version and the reference data which are stored in the target cache region and have the corresponding relationship, thereby solving the technical problems of relatively low data access efficiency and the like caused by the fact that historical snapshot data reading needs to depend on a rear-end disk. The technical effects of cache acceleration of historical snapshot data reading and improvement of data access efficiency are achieved.

The invention relates to an image data writing method and device, computer equipment, a computer readable storage medium and a computer program product. The method comprises the following steps: acquiring to-be-processed image data; according to the storage width of a preprocessing buffer, rearranging the to-be-processed image data to obtain arrangement information; based on the arrangement information, storing the to-be-processed image data to the preprocessing buffer; and when the line number written in the preprocessing buffer reaches a preset line number, writing the to-be-processed image data into a line buffer array from the preprocessing buffer. By adopting the method, the storage efficiency can be improved.

The invention discloses an SSD multi-layer pre-reading method and device, computer equipment and a storage medium, and relates to the technical field of SSD pre-reading. The method comprises the steps that whether a preset pre-reading condition is triggered or not is judged; if the preset pre-reading condition is triggered, loading the data into a multi-layer pre-reading buffer area of the solid state disk; if a read command is received, judging whether the read command hits the multi-layer pre-read buffer area or not; and if the read command hits the multi-layer pre-read buffer area, reading target data corresponding to the read command from the multi-layer pre-read buffer area. According to the method, the NAND inherent cache resources are reused, so that the pre-read data capacity is expanded by multiple times, and hardware cost does not need to be newly increased; when the hit occurs, the physical reading delay of the NAND array is thoroughly avoided, and the traditional serial operation is converted into buffer area direct reading. For a sequential read scene, most read commands skip an NAND access link through multi-stage buffering, and the average delay is compressed from a hundred microsecond level to a microsecond level transmission time, so that the performance step-type improvement is realized.

The invention relates to a message uploading method, a data processing unit and a computer program product, and the method comprises the steps: firstly caching and updating a count after receiving a queue message, determining the number n1 of descriptors needing to be read according to a descriptor index when a queue does not cache a descriptor, reading m1 descriptors (m1 is greater than or equal to n1) from a host side according to cache line alignment, writing the message into a host cache by using n1 descriptors, and updating a count and an index; if the message is processed and the descriptors are left, caching the descriptors which are not used; when the queue has cache descriptors, the cache descriptors are preferentially used for writing messages, if the cache descriptors are not completely written, the number n2 of the descriptors needing to be read is determined according to the descriptor index, m2 (m2 > = n2) descriptors are read from the host side according to cache line alignment to process remaining messages, and if the messages are completely processed and the descriptors are remaining after updating, the descriptors are not used in the same cache. According to the invention, the problem of read delay of the descriptor can be solved, and the overall message processing efficiency is improved.

The invention relates to the technical field of computers, in particular to a method for optimizing the processing speed of a user mode program under an NUMA architecture. The method comprises the steps that in response to the optimization requirement of a user for the processing speed of an original file, first mark information representing the optimization requirement is added in the original file, a target file is generated, and the original file is a user mode program file; registering an interpreter corresponding to the target file; when a starting request corresponding to a target file is received and the starting request is scheduled to the non-uniform memory access node, calling an interpreter to process the target file to obtain a file copy; loading the file copy to a cache space of the non-uniform memory access node; according to the scheme, when the target file is executed, local access can be directly performed, so that delay and performance overhead caused by cross-node access are avoided, and the reading speed and the processing efficiency of the file copy are improved; and while the function complexity is reduced, the system stability is improved, and the system is easier to maintain and manage.

The invention discloses an image processing method based on an FPGA, a storage medium and a computer program product, and relates to the technical field of semiconductor manufacturing. The method comprises the following steps: dividing and expanding a wafer image in a memory of an FPGA according to a convolution effective size and an edge effect size, and determining a target effective matrix and a target reading range of the target effective matrix; and obtaining read data according to the target reading range, and obtaining filling data for filling the target effective matrix located at the edge of the wafer image while obtaining the read data. And performing convolution preprocessing on the acquired data according to the pixel data groups corresponding to the target effective matrixes to obtain target data for executing image processing. Based on the pipeline design of caching the wafer image in the memory, positioning the target reading range and obtaining the filling data during reading, the occupation of the cache space of the memory is reduced, the processing delay of the wafer image is reduced, and the overall image processing efficiency is improved.

The invention discloses a fault tolerance method for key value caches in a model, a product, equipment and a medium, and relates to the technical field of computers, the fault tolerance method comprises the following steps: reading key vectors of a plurality of lexical elements in a key value cache of each layer in a plurality of attention layers layer by layer and detecting, and when it is detected that a reading error exists in a key vector of a first lexical element corresponding to a current layer, determining that the key vector of the first lexical element corresponds to the current layer; and correcting the attention score of the current layer according to the attention importance of the first lexical element in the previous layer, thereby solving the technical problems of poor stability and reliability of model reasoning caused by a key vector reading error in the key value cache, and achieving the purposes of improving the fault-tolerant capability of the key value cache and improving the reliability of the model reasoning. Therefore, the stability and reliability of model reasoning are improved.

In some embodiments, a computer-implemented method for preventing credential passing attacks may include receiving an input; determining whether the input is a credential access command, wherein the determination includes searching for occurrences of references to executables related to adding, reading, copying, or performing actions with respect to a credential, if the input is determined to be a credential access command, performing anomaly detection, wherein performing the anomaly detection includes evaluating whether a user is a valid domain user, whether an elapsed time of the credential is greater than a maximum lifetime of the credential, and whether a privilege attribute certificate of the credential is valid, determining that an anomaly exists if the command was generated by an invalid domain user; an elapsed time of a credential is greater than a maximum lifetime, or the privilege attribute certificate of the credential is invalid, and performing mitigation of the anomaly.

The invention discloses a data pre-reading method, a storage medium and electronic equipment, and relates to the technical field of computers, the data pre-reading method comprises the following steps: determining a target access identifier according to a storage address included in a current data reading request; an access information set matched with the target access identifier is determined, the access information set comprises multiple pieces of access request description information corresponding to the multiple storage sub-areas respectively, and the access request description information is used for indicating the access heat of the corresponding storage sub-areas; under the condition that the access information set comprises current request description information corresponding to the current sub-region and a comparison result between current access heat indicated by the current request description information and reference access heat meets a pre-reading condition, adding at least one second data object read in the current sub-region into a cache, the technical problem of long time consumption in data reading in the prior art is solved.

The invention relates to the technical field of computers, and discloses a distributed block storage system performance optimization method and system.The distributed block storage system performance optimization method comprises the steps that in response to the data storage requirement of a user, the access frequency of data to be stored is analyzed to conduct dynamic blocking, and multiple pieces of block data are generated; dynamically distinguishing data storage nodes into master nodes and slave nodes according to the load state of each node in the storage system; according to the access frequency, writing each piece of block data into a corresponding master node, and copying a data increment corresponding to each master node into a corresponding slave node to obtain an updated master node and an updated slave node; in response to a data reading demand of a user, analyzing access relevance between data, and fusing the updated slave nodes to read corresponding data; according to the method and the device, the data is dynamically partitioned and hierarchically stored, the pressure of the overload main node can be shared, the load condition between the data storage nodes is balanced, and the system performance is optimized.

The invention relates to the technical field of computer data storage and distributed systems, in particular to a distributed read-write method for large model training, which comprises the following steps of: constructing a hierarchical structure of local cache, distributed shared cache and persistent storage, and maintaining a global cache table copy at each client to register file blocks and cache positions. And during writing, firstly writing in a local cache and copying to other client nodes, and submitting persistent storage after registration is completed. During reading, the file blocks are obtained from the local cache and the distributed shared cache in sequence, if the file blocks are not hit, the file blocks are obtained from the persistent storage, meanwhile, the effective file blocks are written back to the local, and table items are supplemented. Unified visibility is achieved through position mapping and version constraint, nearby reading and fault recovery are achieved, back-end pressure and access delay are reduced, and the method is suitable for large-scale training and batch processing scenes.

The invention discloses a dynamic error correction system and method for an OTP (One Time Programmable) memory, a computer and a storage medium, and the system comprises a cross-clock synchronization module which is used for synchronizing asynchronous data of an OTP interface to a system clock domain and generating a control signal according to a data format; the double-buffer-area module is used for alternately writing data and reading a control signal by utilizing two independent buffer areas, and correcting and outputting the written data; the CRC decoder module is used for carrying out error detection on the synchronous data; the error position searching module is used for positioning an error position candidate item of each channel; the error position matching module is used for finding out a uniquely matched error position; and the read control module is used for judging whether data reading needs to be paused or not and starting error correction operation, and sending a control signal to the double-buffer module. According to the invention, a modular architecture design is taken as a core, and a complete processing flow from data receiving, error detection, error positioning to error correction output is constructed.

The invention belongs to the technical field of encoder signal processing, and particularly relates to an encoder capable of realizing non-contact rotation through a measurement magnetic ring of a magnetic induction technology and a TMR magnetic induction read head encoder, performing digital signal processing through a DSP under the driving of a high-speed motor, and integrating signal direct-current bias, amplitude phase difference correction and temperature detection through a program. High-precision position feedback is achieved by subdividing and encoding sine and cosine orthogonal signals inductively output by the measuring magnetic ring, the RS485 protocol communication has the advantages of being high in anti-interference capacity and rich in communication protocol, state monitoring information can be obtained while position information is obtained, motor parameters and encoder parameters can be stored in a built-in mode, and high-precision position feedback can be achieved through a driver. The upper computer is used for reading and modifying, operation is convenient, and the application range is wide.

The embodiment of the invention provides a gateway response method and device and a computer readable storage medium, in a hierarchical storage area comprising a plurality of storage partitions with different storage levels, user characteristics of different users are stored in corresponding storage partitions in the hierarchical storage area according to corresponding storage modes, and when a service request is received, the user characteristics of the different users are stored in the corresponding storage partitions in the hierarchical storage area. According to the method and the device, different storage levels are divided into different storage areas and storage modes, so that the situation that the service request is processed when the user features are more due to a single storage area and a single storage mode can be avoided, and the service request is processed according to the response mode of the service request indicated by the user features. According to the method, the problem of cost waste caused by the user characteristics is solved, the storage cost is reduced, meanwhile, partition reading can be realized when the user characteristics are read through hierarchical storage of the user characteristics, the read-write consumption of the same storage area is reduced, and the reading efficiency is improved.

The utility model belongs to the technical field of computer production testing, and particularly relates to a computer button durability testing device which comprises a vertical plate and a counting assembly, a base assembly is arranged at the bottom of the vertical plate, a fixing block is fixed in the middle of the rear outer wall of the bottom end of the vertical plate, and positioning knobs are in threaded connection with the rear outer wall of the bottom end of the vertical plate in a bilateral symmetry mode. A driving motor is fixedly installed on the outer wall of the middle of the rear portion of the vertical plate, an oval block is fixedly connected to the output end of the driving motor, a counting assembly is fixedly installed in front of the top of the vertical plate, guide rods are fixed to the outer wall of the front portion of the vertical plate in a bilateral symmetry mode, and movable plates are symmetrically arranged on the outer sides of the upper end and the lower end of each guide rod in a sliding mode; a spring is arranged on the outer side of the middle of the guide rod, and the two ends of the spring are fixedly connected with the two movable plates correspondingly. According to the utility model, the pressing column and the isolation plate are synchronously adjusted, so that the counting accuracy can be ensured, the condition of excessive reading or insufficient reading is avoided, and the reliability of a test result is higher.

The present disclosure relates to systems, apparatuses, methods, and non-transitory computer-readable media including a non-volatile memory and a controller operatively coupled to the non-volatile memory. The controller is to determine information on a number of errors for a page for reading data stored in the page of the non-volatile memory, and the data is read using a first read threshold. The controller is to determine a second read threshold based at least in part on the first read threshold and the number of page errors for the page and apply the second read threshold for subsequently reading data stored on the page according to a decision rule.

The invention discloses a reading voltage setting method and device and a storage medium, and relates to the technical field of computer storage, and the method comprises the steps: determining a decoding state based on a reading result of a data reading process, determining error information corresponding to the decoding state, and according to a comparison result of the error information and a preset error threshold value, setting a reading voltage according to the error information. And determining an optimal voltage group according to the current voltage search times of the voltage search process, setting the optimal voltage group as a system reading voltage, setting the preset error threshold as a static configuration parameter, and after the optimal voltage group is determined, dynamically adjusting the preset error threshold according to the error information. According to the method, the reading voltage is dynamically adjusted through the decoding state and the error information of the data reading result, so that the system reading voltage is set, and the system efficiency is further improved.

The embodiment of the invention provides a processor chip verification method, a processor chip verification device, electronic equipment, a computer storage medium and a computer program product. The processor chip verification method comprises the following steps: configuring a fetch field of a fetch register as a slice entry address of a slice entry instruction in a verification program, and configuring a permission state field of a permission state register as a slice entry privilege state corresponding to the slice entry instruction; responding to the slice entry privileged state, and sending a memory access request of at least one preorder instruction of the slice entry instruction; sending a jump request of an enabling field of the permission state register so as to enable an instruction fetching field of the instruction fetching register; and when a completion response of the memory access request is received, executing a reading operation for the slice entry address.