The invention discloses an NAND Flash fault tolerant system based on an FPGA (Field Programmable Gate Array). The NAND Flash fault tolerant system comprises a Flash bad block management subsystem, a USB (Universal Serial Bus) communication subsystem and an upper computer, wherein the Flash bad block management subsystem consists of the FPGA and a Flash array, and is used for detecting factory bad blocks by querying a flag bit of Flash in a spare area, querying return states of a reading operation, a writing operation and an erasing operation to detect lost bad blocks, and recording addresses of all the bad blocks. The Flash is partitioned into three logical areas, namely, a mapping good block area, a bad block area and an information storage area respectively, and an address mapping table is built and stored in the information storage area. The FPGA serves as a core controller, is communicated with the upper computer through the USB communication subsystem, and can receive a control instruction sent by the upper computer and upload data. A usage condition, including a space size of the good block area, a data storage status and the like of a current NAND Flash array can be queried through the upper computer; automatic detection can be performed to update the address mapping table; and stored data in the Flash array can be read, and data can be stored in the Flash array.