NAND Flash fault tolerant system based on FPGA (Field Programmable Gate Array)
A fault-tolerant system and subsystem technology, applied in static memory, instruments, etc., can solve the problems that data cannot be read and written normally, invalid blocks cannot be erased, and Flash is scrapped, so as to solve the problem of bad block detection and management problems, overall performance and processing speed guarantees, and low-cost effects
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[0021] The present invention will be further described below with reference to the drawings and embodiments.
[0022] Such as figure 1 As shown, the FPGA-based NANDFlash fault-tolerant system proposed by the present invention includes a Flash bad block management subsystem, a USB communication subsystem and an upper computer. The Flash bad block management subsystem is composed of FPGA and Flash array. It detects factory bad blocks by querying the flag bit of Flash in sparearea, querying the return status of read, writing and erasing operations to detect lost bad blocks, and records the addresses of all bad blocks. Divide Flash into 3 logical areas, which are mapped good block area, bad block area and information storage area, and establish an address mapping table to store in the information storage area. FPGA, as the core controller, communicates with the host computer through the USB communication subsystem, and can receive control instructions sent by the host computer and up...
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