Hybrid branch prediction device and method for out-of-order high-performance cores

Abstract

The invention discloses a hybrid branch prediction device and method for out-of-order high-performance cores, and relates to the field of computer branch prediction. The device can evaluate the performance of the micro-architecture level of the processor, and reduce out-of-order high-performance processor renaming blockage caused by branch prediction failure and instruction missing; and the deviceprovides a hybrid branch predictor which is high in precision and flexible and configurable in parameterization. The hybrid branch predictor is composed of a global historical information branch TAGEpredictor, a statistical correction predictor and a cycle predictor. According to the TAGE predictor, a parameterized Tagged component and a split reading improvement strategy are utilized, high-precision branch prediction is achieved, and access conflicts are reduced; the statistical correction predictor is used for confirming or restoring the prediction result of the TAGE predictor according tothe prediction result and the confidence coefficient of the TAGE predictor; and the loop predictor is configured to predict a regular loop having a long loop subject using a replacement strategy anda loop branch conversion technique. Limited hardware storage overhead is fully utilized, access conflicts are reduced to a great extent, and the overall performance of the processor is improved whilebranch prediction precision is improved.

Description

technical field [0001] Embodiments of the present invention relate to the field of branch prediction, and in particular to a hybrid branch prediction device and method for out-of-order high-performance cores. Background technique [0002] With the continuous improvement of the performance of the processor core, the processor micro-architecture is also increasingly complex. Faced with increasingly complex processor microarchitecture and limited development time, how to effectively evaluate processor performance has become an important problem to be overcome in processor design. The increase in the number of transistors on a single chip allows the processor to adopt a more complex micro-architecture, and technologies such as superscalar, branch prediction, out-of-order execution, and forward-looking execution are also widely used. However, the problem brought about by the increasingly complex micro-architecture is how to conduct more effective performance analysis in the proc...

AI Technical Summary

Problems solved by technology

[0005] The purpose of the embodiments of the present invention is to provide a hybrid branch prediction device and method for out-of-order high-performance cores, to provide a high-precision hybrid branch predictor, and to solve the problem of low precision in performance analysis of existing processor cores

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