Unified bit width converting structure and method in cache and bus interface of system chip

Abstract

The invention discloses a unified bit width converting structure and method in a cache and a bus interface of a system chip. The converting structure comprises a processor core and a plurality of IP cores carrying out data interaction with the processor core through an on-chip bus, and a memorizer controller IP is communicated with an off-chip main memorizer. The processor core comprises an instruction assembly line and a hit judgment logic unit receiving an operation instruction of the instruction assembly line. An access bit width judgment unit and a bit width/address converting unit are arranged between the hit judgment logic unit and the cache bus interface, the hit judgment logic unit sends a judgment result to the instruction assembly line, and the processor core is connected with the on-chip bus through the cache bus interface. According to the converting method, for the read access of a byte or a half byte, if cache deficiency happens and the access space belongs to the cache area, the bit width/address converting unit converts the read access of the byte or the half byte into one-byte access, access and storage are finished through the bus, an original updating strategy is not affected, and flexibility can exist.

Description

technical field [0001] The invention relates to a data processing structure of a processor core in a system chip and a processing method thereof, in particular to a unified bit width conversion structure of a cache and a bus interface in the system chip and a conversion method thereof. Background technique [0002] In the embedded system chip (SOC), the processor core is responsible for coordinating the orderly work of each IP core. They are integrated together through the on-chip bus, which is conducive to the transplantation and multiplexing of various IP cores and improves the system development. quality and speed. Among them, the AHB high-speed bus protocol introduced by ARM Company is more common on-chip bus. The agreement defines the minimum bus bit width of 32 bits, and stipulates the read and write access timing between the master and the slave. Usually, the access of the processor core to the external memory can include several different bit width forms such as 8-...

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