Cache access method, cache access router and computer system

Abstract

The embodiment of the invention provides a cache access method, a cache access router and a computer system. The cache access method comprises the following steps of: receiving a data packet sent by peripheral equipment by the cache access router, and obtaining the feature information of the data packet, wherein the feature information of the data packet includes any one piece the following information or the combination of the following information including data packet size, packet interval and hot degree information; and storing the data packet into a cache of the processor by the cache access router according to the feature information of the data packet, wherein the cache of the processor comprises at least two stages of caches. The method has the advantages that the data packet is directly stored into the cache; the processor can directly read data from the cache; the number of memory access times is reduced; and the hit rate of the cache is improved, so that the memory access efficiency is improved. The cache of the processor comprises at least two stages of caches; the cache access router can store the data packet into the proper cache according to the feature information of the data packet; and further, the memory access efficiency is improved.

Description

technical field [0001] The embodiments of the present invention relate to communication technologies, and in particular to a cache access method, a cache access router and a computer system. Background technique [0002] With the rapid development of the semiconductor industry, the clock frequency of the processor increases rapidly, but the access speed of the main memory increases much more slowly. The main memory is also called memory. Due to the speed mismatch between processor and memory, memory access latency is still the bottleneck in improving application speed. [0003] In response to the above problems, cache (cache) technology emerged as the times require. Usually, a cache is set between the processor and the memory. By taking out the data that the user may use from the memory and putting it in the cache in advance, when the program wants to call the data, it can Data is read directly from the cache, thus reducing memory access latency. The above method is very e...

AI Technical Summary

Problems solved by technology

However, due to the limited capacity of the third-level cache, storing all data in the third-level cache indiscriminately may cause some commonly used data to be repl

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