Consistency maintenance device for multi-kernel processor and consistency interaction method

Abstract

The invention discloses a consistency maintenance device for a multi-kernel processor and a consistency interaction method, mainly solving the technical problem of large directory access delay in a consistency interaction process for processing read-miss and write-miss by a Cache consistency protocol of the traditional multi-kernel processor. According to the invention, all kernels of the multi-kernel processor are divided into a plurality nodes in parallel relation, wherein each node comprises a plurality of kernels. When the read-miss and the write-miss occur, effective data transcription nodes closest to the kernels undergoing the read-miss and the write-miss are directly predicted and accessed according to node predication Cache, and a directory updating step is put off and is not performed until data access is finished, so that directory access delay is completely concealed and the access efficiency is increased; a double-layer directory structure is beneficial to conversion of directory storage expense from exponential increase into linear increase, so that better expandability is achieved; and because the node is taken as a unit for performing coarse-grained predication, the storage expense for information predication is saved compared with that for fine-grained prediction in which the kernel is taken as a unit.

Description

【Technical field】 [0001] The invention relates to the field of computer technology, in particular to a device and a consistency interaction method for multi-core processor Cache consistency maintenance. 【Background technique】 [0002] Good scalability and efficient use of chip area make CMP processor (Chip Multi-Processor) widely used. However, the electrical characteristics of the wiring on the chip cannot be scaled in proportion to the semiconductor process, and the line delay problem has become an important limiting factor for future CMP designs. Researchers propose a delayed non-uniform Cache access (Non-Uniform Cache Access, NUCA) structure to alleviate the negative impact of line delay on access Cache delay, such as D-NUCA, NuRAPID, Victim Replication, etc. Under the NUCA structure, memory access latency depends on the specific physical distance between the requesting core and the target data. If the target data exists in a core near the requesting core, the average ...

AI Technical Summary

Problems solved by technology

Although this protocol can provide the closest data copy and effectively reduce power consumption, it still needs to access the directory first, and indirect events still exist, and it is difficult to reduce the consistent interaction delay

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