Method and router for processing packets in network on chip

Abstract

The invention provides a method for processing a message in a network-on-chip, and a router. The method comprises the steps that: the router receives a request message sent by a first processor core; the router determines a relationship between an address of a cached response message and an address of the request message, wherein the cached response message comprises a response message of at least one second processor core which is not directly connected to the router; and the router determines a processing manner of the request message according to the relationship. Therefore, the memory access time delay can be reduced, the overall performance of a processor can be improved, and network access overhead can be reduced by utilizing data sharing opportunities of the different processor cores.

Description

technical field [0001] The embodiments of the present invention relate to the computer field, and more specifically, relate to a method and a router for processing packets in a network on chip. Background technique [0002] Due to the separation of processor manufacturers and memory manufacturers in the industrial structure, the development of memory technology and processor technology is not synchronized. In the past 20 years, the performance of the processor has been rapidly improved at a rate of about 55% per year, while the rate of improvement of the memory performance is only about 10% per year. Accumulated for a long time, the unbalanced development speed has caused the current memory access speed to seriously lag behind the processor's calculation speed, and memory bottlenecks have made it difficult for high-performance processors to perform as they should. This requires increasing processing power. This kind of memory bottleneck that seriously hinders the performanc...

AI Technical Summary

Problems solved by technology

Such programming features lead to large Internet applications and long branch jump spans, most of which will exceed the capability range of the processor's L1 or even L2 cache, resulting in a large number of instruction cache misses, so that many application program instructions can only be placed in the In memory and L3 cache

The processor reads instructions from these places far away from the core. Since there is no special through channel, it will cause a large delay and directly affect the performance.

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