FPGA-based high-speed adaptive DVB-S2 LDPC decoder and decoding method

A decoder and self-adaptive technology, which is applied in error detection coding, coding, and code conversion using multi-bit parity bits, and can solve the problem that the decoder does not have the adaptive ability of code rate compatibility.

Active Publication Date: 2017-04-19
XIAN INSTITUE OF SPACE RADIO TECH
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Problems solved by technology

However, some other decoder implementations can achieve higher decoding throughput, but the design itself is only designed for the matrix of a single code rate in the standard, and the decoder does not actually have the adaptive ability of code rate compatibility. , such as: literature (Seok-Min Kim, Chang-Soo Park, and Sun-Young Hwang, "A Novel Partially Parallel Architecture for High-throughput LDPCDecoder for DVB-S2," IEEE Trans.Consumer Electronics, Vol.56, No. 2, May 2010) designe

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  • FPGA-based high-speed adaptive DVB-S2 LDPC decoder and decoding method

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Embodiment Construction

[0036] Adopt the QC-LDPC decoder and the decoding method that improve the node processing parallelism that the present invention proposes, the LDPC code of five code rates that is 16200 with the code length that chooses in the DVB-S2 standard carries out self-adaptive code rate compatible FPGA below High-speed implementation is taken as an example to describe the present invention in detail.

[0037] The H matrix of the LDPC code in the DVB-S2 standard consists of two parts:

[0038] H=[H 1 |H 2 ]

[0039] Among them, H 1 The size is M×K, H 2 is a matrix of lower triangular bidiagonal structure of size M×M, such as figure 1 as shown, figure 2 gives a H for M=36 2 , figure 2 A dot in represents a non-zero element "1". Matrix H 1 The rows are periodic, that is, every q rows (the q values ​​of the five code rates are shown in Table 1) as a whole move one bit to the right to obtain the next q rows, and move 360 ​​times to the right to obtain the parity check matrix h ...

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Abstract

The invention relates to an FPGA-based high-speed adaptive DVB-S2 LDPC decoder and a decoding method. the method comprises steps: (1) matrix transformation is carried out, the generated left matrix has a quasi-cyclic structure, and the right matrix is a new matrix for a triangle-to-dual-diagonal (RTS) sub matrix; (2) RAM and iteration times are initialized; (3) the two parts of matrixes complete variable node information updating and data write back; (4) node information updating and write back are verified, a syndrome vector s is calculated, and one is added to the iteration times iter; (5) if the syndrome vector s is equal to 0 or the maximum iteration times are reached, a sixth step is carried out, or otherwise, the third step is carried out for next-round iteration processing; and (6) a decoding judgment bit is read, and a decoding codeword is outputted.

Description

technical field [0001] The invention relates to an adaptive LDPC decoder technology conforming to the DVB-S2 standard, in particular to an FPGA-based high-speed adaptive DVB-S2 LDPC decoder and a decoding method. Background technique [0002] The second generation of European Digital Satellite Television Broadcasting (DVB-S2) standard provides a high-power and high-spectrum-efficient adaptive coding and modulation scheme, which has been widely used in satellite broadcasting television systems. In order to apply this efficient adaptive coding and modulation scheme to earth exploration satellites, in 2013, the International Space Data System (CCSDS) 131.3-B-1 standard (CCSDS space link protocols over ETSI dvb-s2 standardCCSDS 131.3-b- 1, blue book, march 2013) provides a technical solution for using DVB-S2 standard to transmit CCSDS transmission frames, which solves the format compatibility problem between DVB-S2 and CCSDS. [0003] However, since the maximum transmission rat...

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Application Information

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IPC IPC(8): H03M13/11H03M13/00
Inventor 谢天骄袁瑞佳张国华宋颖
Owner XIAN INSTITUE OF SPACE RADIO TECH
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