Method for managing and allocating buffer storage during Ethernet interchange chip transmission of data

Abstract

A method for managing and allocating buffer in the data transmission procedure of Ethernet switch chip includes allocating the address pointer to input interface module by buffer management module, extracting control information by input interface module, combining it with address. In the buffer management module, there is a release weight table. Each address pointer is relative to a table item. Different release weight values are assigned to different frame control blocks. When frame control blocks are released, the release weight values are decreased until it is equal to zero, that is, all frames are processed.

Description

technical field [0001] The invention relates to electrical digital data processing, in particular to a method for managing and distributing buffers in the data transmission process of an Ethernet switch chip. Background technique [0002] A multi-port Ethernet switch chip that works in a store-and-forward mode first receives all Ethernet data frames that need to be forwarded from the external port and stores them in the shared buffer, and then reads the data frames from the shared buffer according to the forwarding requirements And send it to another external port, the shared cache can be designed inside the switch chip or placed outside the switch chip. [0003] In the existing data cache processing, such as figure 1 As shown, the Ethernet data frame entering the switch chip from the external port applies for caching to the cache management module at the input interface, and the cache management module feeds back a free cache address pointer to the input interface module a...

AI Technical Summary

Problems solved by technology

[0016] 1. The number of visits to the multicast reference counting table is relatively large: in the whole process of data frame processing, the multicast reference counting table needs to be accessed in operations such as initialization, application for allocation, application for refresh, and application for release, which makes the multicast reference counting table The timing design of the counting table is very tight. In order to meet the processing speed requirements of the high-speed Ethernet switching chip, a relatively expensive and complicated circuit design scheme has to be adopted, which increases the cost of the switching chip.

[0017] 2. The processing of stacked speed data frames is inconsistent with that of ordinary data frames, which increases the complexity of data processing and circuit design

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