56results about How to "Improve decoding throughput" patented technology

A method of performing decoding using an LDPC code is disclosed. The method of performing decoding an encoded codeword using a parity check matrix, comprises decoding the codeword using the parity check matrix, wherein the parity check matrix includes a plurality of layers, each of which includes at least one or more rows split exclusively from a specific row of a base parity check matrix.

The invention discloses a multiple-rate, quasi-cycling and low density decoder for parity check codes, comprising a variable node information memory bank, a check matrix information memory bank, a symbol memory bank, an intermediate information memory bank, a variable node processor set, a check node processor set and a shifter set. The decoder uses two adjacent submatrixes as the basic unit of the check node update and the variable node update to perform concurrent operation, thereby greatly enhancing the throughput rate of coding; meanwhile due to that the QC-LDPC codes with different code rates share the same memory unit and hardware resource, the decoder realizes the full multiplexing of hardware units such as check node processors and variable node processors, the structure of the decoder can be designed regardless of the specific code rate, and the decoding with multiple rates is realized by using the hardware resource of single code rate, thereby enhancing the use ratio of the hardware.

Rapid throughput of still image compressed data (e.g. JPEG) is achieved for presentation of images in rapid succession for browsing or browsing by panning within large images by using a hardware decoder adapted for presentation of moving images to reduce the processing load which must be performed in accordance with software although the still image data is incompatible with still image data in many respects; some of which necessarily lead to a loss of image fidelity. The still image data is partially decoded (e.g. entropy decoded) in software processing and re-encoded and reformatted to a form which can at least be accepted by the hardware decoder even though not compliant with any particular moving picture data standard (e.g. MPEG). Storage in the hardware decoder is reallocated to provide, in combination with a reduction of slower software processing, a throughput increase of four-fold or more. Software processing of the still image data is also allowed to proceed and the result substituted for the result of the hardware decoding if a given image is viewed for a time sufficient for the software image processing to be completed.

Systems, methods, and apparatus are provided for increasing decoding throughput in an LDPC decoder, such as in a wireless communications receiver or in a data retrieval unit. A checker-board parity check matrix and edge-based LDPC decoder structure are provided in which both vertical and horizontal processors are used simultaneously. Horizontal processors may be grouped into type-A and type-B horizontal processors, and similarly, vertical processors may be grouped into type-A and type-B vertical processors. Type-A processors may be used in different clock cycles than type-B processors to update memory locations in a decoding matrix without causing memory access conflicts.

The invention discloses an LDPC (low density parity check) decoding optimization method based on flash programming interference error perception. Along with the increase of NAND flash-memory storage density, more bit information is stored in each unit; the coupling interference along the units is high; the serious programming interference errors are caused, so that the traditional BCH code cannot ensure the data reliability; the LDPC code has error-correcting performance superior to that of the BCH code, and is applied to an NAND flash-memory storage system. The used optimized LDPC decoding algorithm has important significance. Through observation, the programming interference errors have value correlative characters; when the LDPC decoding is performed, the value correlative characters of the programming interference errors can be blended into the LDPC decoding process; the additional information is provided for bit judgment, so that the bit judgment precision is improved; the decoding convergence speed is accelerated; the LDPC decoding delay is reduced.

The invention discloses a parallel multicode-rate convolutional code decoding method and a realization device thereof. The parallel multicode-rate convolutional code decoding method comprises the following steps of: S1. receiving Nin paths of parallel input signals, and shifting the input signals under the effect of a shifting control signal and outputting the input signals, wherein output signals are also Nin paths of parallel signals, and the Nin is positive integers; S2. partially eliminating the phase ambiguity of the output signals; S3. taking the signals processed in the S2 as effectivedata, adding guard intervals for the effective data to assemble into a data frame, and taking the data frame as the input of a parallel convolutional code; S4. carrying out the convolutional decodingon the assembled data frame after being processed in the step S3; and S5. merging multipath outputs of the parallel convolutional decoding into one path and outputting in parallel. The invention provides the parallel multicode-rate convolutional code decoding method aiming at the defect that the throughput rate of the traditional convolutional decoding can not satisfy high-speed communication, improves the decoding throughput rate and the effective payload velocity by adopting a parallel partitioning processing technology, and can satisfy requirements of high-velocity information transmissioncommunication systems, such as satellite communication, and the like.

The invention discloses a general high-performance Radix-4SOVA decoder and a decoding method. In the prior art, in the Radix-4SOVA decoder, only a binary system Turbo code based on bit interleaving is supported. By using the decoder and the method of the invention, the above problem is mainly solved. The method has the following steps of receiving channel information and storing; reading the channel information of a first component code, carrying out first component decoding which means that a branch metric, a cumulative path metric, credibility, a log-likelihood ratio and extrinsic information are successively calculated, interleaving the extrinsic information and storing; reading the channel information of a second component code and completing secondary component decoding; determining whether a maximum iteration is reached; if the maximum iteration is not reached, starting next iteration decoding; otherwise, carrying out hard decision on the log-likelihood ratio so as to obtain an estimation value of a decoding bit and finishing the decoding. According to the invention, a credibility updating method based on a bit pair is used; the general and configurable high performance decoding of a binary system Turbo code and a duobinary system convolution Turbo code can be realized; the method can be used in a general and configurable Turbo decoder in a LTE and WiMAX system.

The invention discloses a high-speed code rate compatible LDPC encoder of a QC-LDPC code based on an FPGA. The method comprises the following steps of sending a column vector of a component of each information sub-block of an input information sequence to a check bit calculation module through a control module; performing time delay on a column vector of a component of the information sub-block through a delay module, and sending the column vector to a selective shift output module; enabling the shift operation module to determine a shift method of the cyclic shift register according to the code rate rate rate of the encoder, and send the shift method to the cyclic shift register; According to a shift method for determining the cyclic shift register, performing shift operation on the firstrow data bi, j (0) of the cyclic sub-matrixes Bi, j, calculating to obtain a check vector according to a result after the shift operation and information bit by bit of an input information bit sequence, and sending the check vector to a selective shift output module; And selecting a shift output module, and outputting the check vector and the column vector of the component of the information sub-block at different times. The high-speed code rate compatible encoder architecture disclosed by the invention can realize resource sharing between different code rates to the greatest extent.

An operating method applied to low density parity check (LDPC) decoders and the circuit thereof are proposed, in which original bit nodes are incorporated into check nodes for simultaneous operation. The bit node messages are generated according to the different between the newly generated check messages and the previously check node messages. The bit node messages can be updated immediately, and the decoder throughput can be improved. In the other way, the required memory of LDPC decoders can be effectively reduced, and the decoding speed can also be enhanced.

The invention provides an LDPC (low density parity check) decoder and an LDPC decoding method. The LDPC decoder comprises a variable update node module, a check update node module, a global interconnection module and a control unit, wherein the variable update node module comprises M variable update node calculation units which are used for carrying out variable node update calculation on an inputted message, thereby acquiring an updated message of variable nodes; the check update node module comprises N check update node calculation units which are used for carrying out check node update calculation on the inputted message, thereby acquiring updated message of check nodes; the global interconnection module is used for mutually connecting each of the M variable update node calculation units and each of the N check update node calculation units; and the control unit is used for carrying out control, thereby enabling the acquired updated message of the variable nodes to be transmitted to each of the N check update node calculation units, enabling the updated message of the check nodes to be transmitted to each of the M variable update node calculation units, and being capable of decoding two different code words parallelly.

The invention discloses a quantum key distribution random low-density parity-check (LDPC) code parallel decoding method. The method comprises the following steps: S1, performing initialization: loading two key strings, namely key0 and key1, from a key string storage module, and finishing variable node decoding of the key0; S2, calculating key0 check node information and key1 variable node information; S3, performing a key0 hard decision calculation; S4, loading the key0: loading a new key string into an LDPC decoder key0 buffer area from the key string storage module; S5, calculating key1 check node information and key0 variable node information; S6, performing a key1 hard decision calculation; and S7, loading the key1: loading a new key string into a decoder key1 buffer area from the key string storage module. The method has the advantage that the overall efficiency and performance can be improved.

The invention discloses a method for decoding LDPC codes. The method for decoding the LDPC codes includes the following steps of determining a multiplexed line of a check matrix, determining a first check node calculation part, a second check node calculation part, a first variable node calculation part and a second variable node calculation part of a decoding unit, subjecting the multiplexed line to a first processing in the K times iteration processing, subjecting the first variable node calculation part to a K-1 times variable node update calculation when the first check node calculation part is subjected to a K times check node update calculation, subjecting the multiplexed line to a second processing, and subjecting the second check node calculation part to a K times check node update calculation while the second variable node calculation part is subjected to a K times variable node update calculation. Compared with the sequence of the variable node calculation and the check node calculation in the traditional method, the method for decoding the LDPC codes improves the decoding handling capacity of the LDPC codes.

A decoding method of low-density parity-check (LDPC) codes based on partial average residual belief propagation includes the following steps: S1: calculating a size of a cluster π in a protograph based on a code length m and a code rate of a target codeword; S2: pre-computing an edge residual r_{c<sub2>i</sub2>→v<sub2>j </sub2>}corresponding to each edge from a variable node to a check node in a check matrix H; S3: calculating, based on π, a partial average residual (PAR) value corresponding to each cluster in the check matrix H; S4: sorting m/π clusters in descending order of corresponding PAR values, and updating an edge with a largest edge residual in each cluster; S5: updating edge information m_{c→v<sub2>i </sub2>}from a check node c_i to a variable node v_j, and then updating a log-likelihood ratio (LLR) value L(v_j) of the variable node v_j; and S6: after the updating, making a decoding decision.