58results about How to "Improve decoding throughput" patented technology

Rapid throughput of still image compressed data (e.g. JPEG) is achieved for presentation of images in rapid succession for browsing or browsing by panning within large images by using a hardware decoder adapted for presentation of moving images to reduce the processing load which must be performed in accordance with software although the still image data is incompatible with still image data in many respects; some of which necessarily lead to a loss of image fidelity. The still image data is partially decoded (e.g. entropy decoded) in software processing and re-encoded and reformatted to a form which can at least be accepted by the hardware decoder even though not compliant with any particular moving picture data standard (e.g. MPEG). Storage in the hardware decoder is reallocated to provide, in combination with a reduction of slower software processing, a throughput increase of four-fold or more. Software processing of the still image data is also allowed to proceed and the result substituted for the result of the hardware decoding if a given image is viewed for a time sufficient for the software image processing to be completed.

A memory address generation method and circuit architecture for time-multiplexed RS-based LDPC code decoder is presented. The method is developed for non quasi-cyclic RS-based LDPC code decoder implementation. A circuit for the memory address generation method achieves low area. High throughput time-multiplexed RS-based LDPC code decoder design models and circuit architectures are presented. The decoder models are specifically developed for 10BASE-T (10-Gigabit Ethernet Transceiver Over Copper) system. These time-multiplexed architectures enable higher throughput with lower area.

A method of performing decoding using an LDPC code is disclosed. The method of performing decoding an encoded codeword using a parity check matrix, comprises decoding the codeword using the parity check matrix, wherein the parity check matrix includes a plurality of layers, each of which includes at least one or more rows split exclusively from a specific row of a base parity check matrix.

An operating method and a circuit for low density parity check (LDPC) decoders, in which original bit nodes are incorporated into check nodes for simultaneous operation. The bit node messages are generated according to the difference between the newly generated check messages and the previous check node messages. The bit node messages can be updated immediately, and the decoder throughput can be improved. The required memory of LDPC decoders can be effectively reduced, and the decoding speed can also be enhanced.

The invention provides high-speed parallel Turbo decoding method and system in a software radio system. The method comprises the following steps: dividing data to be decoded into M segments, and reordering the data to continuously store the corresponding data at the same positions in the M segments; carrying out iterative decoding on the reordered data to be decoded, comprising the processes of performing parallel component code decoding on the data in the M segments and performing interlacing and de-interlacing on the exchange external information of the two component codes through an interlacing list calculated in advance; and calculating the log likelihood of a system bit, performing symbol judgment, and reordering the judged decoding bit sequences to recover the natural sequence. According to the embodiment of the invention, the high-speed parallel Turbo decoding in the software radio system is realized, the decoding time is greatly reduced and the decoding throughout rate is improved.

The invention provides an accelerated QC-LDPC (Quasi-Cyclic Low-Density Parity-Check Code) decoding method based on a GPU (Graphics Processing Unit) framework. The method comprises the steps of: taking a CPU (Central Processing Unit) as a controller, calculating code word information of an input code by using a mother matrix of the input code, placing the code word information in a constant storage of a GPU, and starting a GPU core function running command after all initializing processes are finished; and reasonably configuring various parameters of the GPU, realizing a whole decoding system in each GPU parallel thread block, and finishing LDPC decoding based on a layered revising minimum sum algorithm by the cooperation among threads. According to the method, the universal accelerated decoding on QC-LDPCs with different code rates under different GPU platforms can be realized according to the characteristics of LEPC words in a QC structure; a plurality of LDPC decoders which can be realized and optimized on the GPU in a parallelization manner, and can independently run on the GPU in the parallelization manner can be provided; and the decoding efficiency is improved greatly, so that the accelerated QC-LDPC decoding method can be effectively applied to a simulated and real-time decoding system.

A system providing early termination for channel decoding by re-encoding including a decoding unit, an encoding unit connected to the decoding unit, and a checking unit connected to the decoding unit and to the encoding unit. Via the system, decoded message words produced from the decoding unit are sent back to the encoding unit for re-encoding. Re-encoded words are compared to the decoded codewords by the checking unit and, if they are completely the same, the decoding action of the decoding unit is terminated. The system reduces power consumption and offers a simplified structure, improved decoding throughput, and reduced hardware complexity.

The invention belongs to the technical field of wireless communication and micro-electronics, in particular to an ultrahigh-speed low-power-consumption and low-density parity check code (QC-LDPC) decoder based on TDMP. Through symmetrizing six grades of production lines, interlacing row blocks and line blocks, re-sequencing nonzero sub matrixes, carrying out four-quadrant division on a sum value register pile and adopting the technology of reading and writing the bypass, the decoder carries out serial scanning in the row sequence, two nonzero sub matrixes are respectively processed in each clock period during horizontal updating and vertical updating. The horizontal updating and the vertical updating are fully overlapped. Particularly, the sum value register pile stores the sum values of variable nodes, and is also used as an FIFO for storing transient external information transferred between two phases. The structure of the decoder has strong configurability, can be easily transplanted into any other irregular or irregular QC-LDPC codes, and has the excellent decoding performance, the peak frequency can reach 214 MHz, the thuoughput can reach about 1 gigabit per second, and the chip power consumption is only 397 milliwatts.

The invention discloses a method for decoding LDPC codes. The method for decoding the LDPC codes includes the following steps of determining a multiplexed line of a check matrix, determining a first check node calculation part, a second check node calculation part, a first variable node calculation part and a second variable node calculation part of a decoding unit, subjecting the multiplexed line to a first processing in the K times iteration processing, subjecting the first variable node calculation part to a K-1 times variable node update calculation when the first check node calculation part is subjected to a K times check node update calculation, subjecting the multiplexed line to a second processing, and subjecting the second check node calculation part to a K times check node update calculation while the second variable node calculation part is subjected to a K times variable node update calculation. Compared with the sequence of the variable node calculation and the check node calculation in the traditional method, the method for decoding the LDPC codes improves the decoding handling capacity of the LDPC codes.