This invention discloses an LDPC decoder belonging to the field of channel coding and decoding technology. In some scenarios of modern communication, LDPC decoders require high
throughput but consume significant hardware resources. This invention designs an ultra-high
throughput LDPC decoder based on a shift-based basis graph. The decoder instantiates multiple decoders internally, and the decoder core uses an LDPC parity-check matrix based on a shift-based basis graph, employing a row-grouped minimum sum decoding
algorithm for decoding. The advantages of this invention are: using an LDPC parity-check matrix based on a shift-based basis graph to design the
decoder architecture reduces the hardware
resource consumption of the read and write-back modules in the row-grouped decoder, reduces the decoder area, effectively improves the
throughput per unit area, and significantly improves the
decoding throughput through multi-core parallel decoding.