Accelerated decoding method of qc-ldpc code based on gpu architecture

A GPU architecture and decoding technology, applied in the field of decoding systems, can solve the problems of high complexity and cost, low versatility and configurability, long development cycle, etc., to achieve easy implementation, improve decoding throughput, and achieve The effect of parallelization

Active Publication Date: 2016-05-04
SHANGHAI JIAOTONG UNIV
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Problems solved by technology

Since this method uses FPGA hardware to implement, it needs to consider more timing issues and resource allocation issues, which has high complexity and cost and requires a long development cycle; and the versatility and configurability are not high.

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  • Accelerated decoding method of qc-ldpc code based on gpu architecture
  • Accelerated decoding method of qc-ldpc code based on gpu architecture
  • Accelerated decoding method of qc-ldpc code based on gpu architecture

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Embodiment Construction

[0057] The present invention will be described in detail below in conjunction with specific embodiments. The following examples will help those skilled in the art to further understand the present invention, but do not limit the present invention in any form. It should be noted that those skilled in the art can make several modifications and improvements without departing from the concept of the present invention. These all belong to the protection scope of the present invention.

[0058] Such as figure 1 Shown is a schematic diagram of the structure of the H matrix of the QC-LDPC code constructed by the quasi-cyclic extension method. Take the WiMAX codeword with a code length of 2304 and a code rate of 0.5 as an example, input the mother matrix of the decoded code word, calculate the check matrix with a maximum row weight of 7, a maximum column weight of 6, code length N=2304, code rate R=0.5, QC expansion factor Z_f=96.

[0059] Such as figure 2 As shown, a schematic d...

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Abstract

The invention provides an accelerated QC-LDPC (Quasi-Cyclic Low-Density Parity-Check Code) decoding method based on a GPU (Graphics Processing Unit) framework. The method comprises the steps of: taking a CPU (Central Processing Unit) as a controller, calculating code word information of an input code by using a mother matrix of the input code, placing the code word information in a constant storage of a GPU, and starting a GPU core function running command after all initializing processes are finished; and reasonably configuring various parameters of the GPU, realizing a whole decoding system in each GPU parallel thread block, and finishing LDPC decoding based on a layered revising minimum sum algorithm by the cooperation among threads. According to the method, the universal accelerated decoding on QC-LDPCs with different code rates under different GPU platforms can be realized according to the characteristics of LEPC words in a QC structure; a plurality of LDPC decoders which can be realized and optimized on the GPU in a parallelization manner, and can independently run on the GPU in the parallelization manner can be provided; and the decoding efficiency is improved greatly, so that the accelerated QC-LDPC decoding method can be effectively applied to a simulated and real-time decoding system.

Description

technical field [0001] The invention relates to a decoding system in the technical field of digital signal processing, in particular to an accelerated decoding method of a quasi-cyclic low-density parity-check code (QCLDPC). Background technique [0002] Low Density Parity Check Codes (LowDensityParityCheckCodes, LDPCodes) is an error correction code first proposed by Gallager in 1963. It has performance close to Shannon's limit and is widely used in various wireless communication standards, including China's digital TV terrestrial Transmission standards, European second-generation satellite digital video broadcasting standards, IEEE802.11n, IEEE802.16e, etc. This technology is also widely used in magnetic storage systems and optical fiber communications. [0003] Quasi-Cyclic Low Density Parity Check Code (Quasi-Cyclic LDPC, QCLDPC) is a kind of LDPC code whose parity check matrix is ​​composed of a small zero square matrix and a small cyclic matrix. One of the most practi...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H03M13/11
Inventor 王帆杨艺宾俞晖黄正勇
Owner SHANGHAI JIAOTONG UNIV
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