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high-speed code rate compatible LDPC encoder of a QC-LDPC code based on an FPGA

A code rate compatible, encoder technology, applied in error detection coding using multi-bit parity bits, error correction/detection using block codes, data representation error detection/correction, etc. Variable bit rate compatible design, low encoder throughput, etc.

Active Publication Date: 2019-05-24
XIAN INSTITUE OF SPACE RADIO TECH
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

There are relatively few studies on this type of encoder. The throughput of this kind of encoder based on the generator matrix is ​​generally low, and the frame-by-frame variable code rate compatibility design issue is rarely considered.

Method used

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  • high-speed code rate compatible LDPC encoder of a QC-LDPC code based on an FPGA
  • high-speed code rate compatible LDPC encoder of a QC-LDPC code based on an FPGA
  • high-speed code rate compatible LDPC encoder of a QC-LDPC code based on an FPGA

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Embodiment Construction

[0077] The present invention will be further described in detail below in conjunction with the accompanying drawings and specific embodiments.

[0078] A high-speed code rate compatible LDPC encoder based on the FPGA-based QC-LDPC code of the present invention sends the column vector of the components of each information sub-block of the input information sequence to the check bit calculation module through the control module; the information sub-block The column vector of the component is time-delayed by the delay module and then sent to the selection shift output module; the shift operation module determines the shift method of the cyclic shift register according to the code rate rate of the encoder, and sends it to the cyclic shift register ;According to the shift method of determining the cyclic shift register, the cyclic sub-matrix B i,j The first row of data b i,j (0) Carry out the shift operation, calculate the check vector according to the result after the shift oper...

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Abstract

The invention discloses a high-speed code rate compatible LDPC encoder of a QC-LDPC code based on an FPGA. The method comprises the following steps of sending a column vector of a component of each information sub-block of an input information sequence to a check bit calculation module through a control module; performing time delay on a column vector of a component of the information sub-block through a delay module, and sending the column vector to a selective shift output module; enabling the shift operation module to determine a shift method of the cyclic shift register according to the code rate rate rate of the encoder, and send the shift method to the cyclic shift register; According to a shift method for determining the cyclic shift register, performing shift operation on the firstrow data bi, j (0) of the cyclic sub-matrixes Bi, j, calculating to obtain a check vector according to a result after the shift operation and information bit by bit of an input information bit sequence, and sending the check vector to a selective shift output module; And selecting a shift output module, and outputting the check vector and the column vector of the component of the information sub-block at different times. The high-speed code rate compatible encoder architecture disclosed by the invention can realize resource sharing between different code rates to the greatest extent.

Description

technical field [0001] The invention relates to a high-speed code rate compatible LDPC encoder based on an FPGA-based QC-LDPC code, and belongs to the technical field of high-speed code rate compatible encoders. Background technique [0002] With the development of my country's space technology and communication technology, remote sensing satellites, communication satellites, relay satellites, as well as deep space exploration, manned spacecraft and space stations, have increasingly urgent needs to increase satellite data transmission rates. In terms of channel coding, traditional RS codes, convolutional codes, and concatenated codes can no longer meet the requirements of data transmission systems for parameters such as coding gain, coding efficiency, and throughput. LDPC codes have been widely used in satellite data transmission systems at home and abroad because of their high error correction performance, low error floor, relatively simple hardware implementation, and easy...

Claims

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Application Information

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IPC IPC(8): H03M13/11
CPCY02D30/70
Inventor 谢天娇袁瑞佳宋颖胡西阁左金钟
Owner XIAN INSTITUE OF SPACE RADIO TECH
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