Multiple-rate, quasi-cycling and low density decoder for parity check codes

Abstract

The invention discloses a multiple-rate, quasi-cycling and low density decoder for parity check codes, comprising a variable node information memory bank, a check matrix information memory bank, a symbol memory bank, an intermediate information memory bank, a variable node processor set, a check node processor set and a shifter set. The decoder uses two adjacent submatrixes as the basic unit of the check node update and the variable node update to perform concurrent operation, thereby greatly enhancing the throughput rate of coding; meanwhile due to that the QC-LDPC codes with different code rates share the same memory unit and hardware resource, the decoder realizes the full multiplexing of hardware units such as check node processors and variable node processors, the structure of the decoder can be designed regardless of the specific code rate, and the decoding with multiple rates is realized by using the hardware resource of single code rate, thereby enhancing the use ratio of the hardware.

Description

technical field [0001] The invention relates to a decoder structure, in particular to a multi-code-rate quasi-cyclic low-density parity-check code decoder. Background technique [0002] Low Density Parity Check (LDPC, Low Density Parity Check) code is a linear block code that can be described by a very sparse parity check matrix. It was first proposed by Gallager of the Massachusetts Institute of Technology in the 1960s. LDPC code not only has excellent performance close to the Shannon limit, but also has low decoding complexity, so it has attracted much attention in recent years and has become the encoding method selected by communication standards such as DVB-S2 and IEEE 802.16e. [0003] Quasi-Cyclic Low Density Parity Check (QC-LDPC, Quasi-Cyclic LDPC) code is a special LDPC code, because its generator matrix G and parity check matrix H have quasi-cyclic characteristics, it is not only convenient for hardware implementation, but also Maintain good decoding performance. ...

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Problems solved by technology

[0008] 1) Since the decoding algorithm used is the log-BP algorithm, the update of the check node and the update of the variable node are performed separately, resulting in a large decoding delay;

[0009] 2), the log-BP algorithm is relatively difficult to implement in hardware, and the complex Ψ function is implemented by looking up a table, which occupies a large area;

[0010] 3) The row weights and column weights corresponding to check matrices of different code rates are very different. However, this scheme configures check node operation units and variable node operations according to t

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