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Forward error correction decoding decoder based on burst error detection

A forward error correction and burst error technology, applied in the field of forward error correction decoder architecture, can solve the problems of low decoding efficiency, low throughput rate, waste of hardware resources, etc., so as to shorten the decoding time and improve the throughput. rate, the effect of shortening the delay

Pending Publication Date: 2020-04-07
TIANJIN UNIV
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Problems solved by technology

[0005] Note that in the existing hard-decision decoder architecture, the delay of the syndrome calculation module and the money search and error estimation module is n (n is the RS code packet length) clock cycles, and the minimum delay of the KES module is 2t-1 clock cycle, so there is a lot of idle time in the KES module, which causes a waste of hardware resources. The directly implemented decoder occupies a large area, has low throughput, and low decoding efficiency.

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  • Forward error correction decoding decoder based on burst error detection
  • Forward error correction decoding decoder based on burst error detection
  • Forward error correction decoding decoder based on burst error detection

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Embodiment Construction

[0025] A four-degree parallel forward error correction decoder (RS-FEC) architecture for the RS decoding algorithm-mCS-RiBM algorithm. The improvements include the following aspects:

[0026] (1) The function of the SC module is implemented using a parallel structure. From the perspective of reducing the critical path, the syndromes are divided into odd parts and even parts to be calculated separately, and finally summed to calculate 2t syndromes. The parallelism factor of the syndrome calculation circuit is 4, and the symbols of each channel are input in order from high to low. In one clock cycle, the syndrome calculation module processes 4 symbols at the same time. After n / 4 After the clock cycle, the calculated syndrome is sent to the KES module;

[0027] (2) Since the number of channels of the sub-decoder is 4, it is necessary to increase the 1 pair of registers of each processing unit in the original KES module to 4 pairs. Ordinary multipliers are replaced with pipeline ...

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Abstract

The invention belongs to the field of error control coding in channel coding, and aims to shorten the delay of a critical path of a decoder on the premise of ensuring the decoding performance so as toimprove the decoding throughput rate. Therefore, the technical scheme adopted by the invention is as follows. The invention discloses a forward error correction decoding decoder based on burst errordetection which comprises a syndrome calculation SC module, a key equation solving KES module and a money search and error estimation CSEE module. A syndrome calculated by the SC module is output to the KES module, and an error position polynomial lambda (X) and an error estimation polynomial omega (X) calculated by the KES module are output to the CSEE module. The decoder is mainly applied to decoder design and manufacturing occasions.

Description

technical field [0001] The invention belongs to the field of error control coding in channel coding, and Reed-Solomon (Reed-Solomon, RS) coding and decoding related technologies, pipeline technology, and retiming technology, in particular to Reed-Solomon (RS) code RS(255,239 ) Forward error correction decoder architecture suitable for 100Gb / and above rate optical communication systems. Background technique [0002] In recent years, the development of communication technology has made the transmission of digital information more and more frequent. Digital signals are transmitted in time and space through wired or wireless media or storage devices. However, due to the unsatisfactory transmission channels, digital signals are transmitted Errors occur due to different degrees of noise interference during the process. Error control coding is a technology that corrects the errors generated in the transmission process through coding and decoding technology in the process of digit...

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H03M13/15
CPCH03M13/1515
Inventor 张为王佳琪陆薇
Owner TIANJIN UNIV
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