High speed bit flat surface decoding method and circuit suitable for Jpeg2000 standard

Abstract

The invention discloses a method and an electric circuit structure for bit plane quick decoding of EBCOT coefficient in coding and decoding standard of ISO / IEC JPEG2000 image compressing so as to improve JPEG2000 EBCOT decoding efficiency. The position plane decoding electric circuit of the invention can make the original coding block expansion analog pixel to form a new coding block being divided into three bank storage coefficients and coefficient state information, so the invitation capacity of a storage can be reduced, the coefficient can be scanned by using 6x4 window to accelerate the decoding process, simultaneously, a parallel technology is used to further improve the total EBCOT decoding throughput. The invention can improve JPEG2000 image decoding efficiency and can be widely used in digital image product series.

Description

technical field [0001] The invention proposes a bit-plane decoding method and circuit implementation for the JPEG2000 standard. The circuit is a part of a high-speed EBCOT decoder and is widely used in computer network applications, digital cameras, video cameras and other fields. Background technique [0002] With the development of multimedia technology, the current image compression technology not only requires high compression performance, but also requires new features to meet some special needs, such as retaining high compression while achieving a low bit rate. Quality, can have lossy and lossless compression methods at the same time, can support image partial codec processing, support image quality progressive transmission, etc. These requirements make the JPEG2000 standard emerge as the times require. JPEG2000 is a multi-analysis encoding method based on discrete wavelet transform. [0003] Since the publication of the JPEG2000 standard, many documents have analyzed...

AI Technical Summary

Problems solved by technology

[0008] Since the code stream input to the decoder has a certain pass order during decoding, that is, according to the order of the importance expansion channel, the amplitude refinement channel and the clearing channel, the coefficient bits solved during decoding are not for each coding block The strips of each bit plane are sequential, so it is very difficult to implement a mechanism for parallel processing of encoding channels, and the hardware complexity is very high. Serial decoding makes decoding efficiency very low, and the decoding engine continuously generates CX. It scans the solved coefficients according to the decoding order of the three passes, and continuously judges which pass the next coefficient bit belongs to, and whether it meets the solvable conditions, which wastes many clock cycles

Since the inverse quantization coefficients of each sub-band at the same level are ready for wavelet inverse transform processing, therefore, a decoding of the entire tile using only the BPD module will inevitably have a bottleneck

When multiple BPDs are processed in parallel, the processing speeds of each BPD are inconsistent, so that the fast decoding BPD will wait for the slow decoding BPD, and the BPD that has completed decoding cannot be started to start the decoding of the next code block. reduces work efficiency

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