43 results about "Timing diagram" patented technology

A method and system are provided for timing analysis of an electronic circuit design. A timing graph defines a plurality of timing paths through different subsections of the electronic circuit design. A timing window is defined for each of the nodes included in a timing path. At least one preliminary round of a predetermined signal integrity analysis is executed on the circuit design based on the timing windows to identify at least one pair of crosstalk-coupled victim and aggressor nodes. Each victim node's timing window is adaptively adjusted according to a predetermined timing property thereof. At least one primary round of the predetermined signal integrity analysis is executed on the electronic circuit design based in part on this adaptively adjusted timing window for each victim node to generate a delay, which is annotated to the timing graph. A predetermined static timing analysis is executed based on the delay-annotated timing graph.

The invention discloses a node representation method based on a sequential graph neural network and an incremental learning method, and belongs to the technical field of graph representation learning. After the preprocessing operation, a GCN model with a double attention mechanism is used for respectively processing the time sequence graph snapshots at different moments, graph convolution calculation is carried out, and the structure embedding representation of any node at any moment is obtained; inputting the structure embedded representation of any node at each moment into a t-GRU time sequence network as a sequence to perform serial calculation, and solving a final embedded representation of any node at any moment; for the new data at the T moment, storing an intermediate result before the T moment; only one GCN model with a double attention mechanism being used for processing incremental graph data at the moment T; and synthesizing the intermediate result and the T moment result into a sequence, and inputting the sequence into a t-GRU time sequence network for serial calculation to obtain embedded representation of any node at the T moment. The method is suitable for various time sequence diagram scenes, node representation information is richer and more accurate, and the model iteration convergence speed is high.

The invention relates to a data cleaning method and device and a computer readable storage medium. The method comprises the steps of obtaining structured data and aging constraints, establishing a time sequence diagram for all tuples, and obtaining an aging sub-diagram through a transfer protocol; calculating an aging value of each tuple based on the time sequence sub-graph; taking the timeliness-consistency joint repair distance as an index, calculating an editing distance between the error tuple and the high-quality tuple, and selecting a repair mode which meets consistency rule constraintsand is closest to the timeliness value of the error tuple to perform consistency repair on the error tuple; utilizing a Bayesian filling method, taking the aging value of the tuple as a newly added attribute of the tuple to participate in a Bayesian training process, and realizing filling of a missing value; and obtaining a cleaned data set. According to the method, three data quality problems ofunavailable timestamps, incomplete attribute values and inconsistent attribute values existing in a data set at the same time can be effectively identified and repaired.

The invention discloses a static timing sequence analysis method based on distribution. The method comprises the following steps: establishing a timing sequence diagram and grouping; finding out a to-be-split time sequence diagram in each group of time sequence diagrams, and splitting the to-be-split time sequence diagram into a plurality of time sequence sub-diagrams; searching a to-be-split timesequence diagram in each group of time sequence diagrams, and splitting the to-be-split time sequence diagram into a plurality of time sequence sub-diagrams; reading design data of time sequence analysis for each group of time sequence diagrams of the new group; and carrying out static timing analysis on each group of timing diagrams of the new group in parallel. According to the static timing sequence analysis method based on distribution, after the timing sequence diagram is split, the efficiency of parallel computing of the timing sequence diagram is greatly improved compared with that before splitting.

The invention discloses a traffic speed prediction method based on a time sequence diagram neural network, and the method comprises the following steps: S1, collecting the observation data of a traffic speed sensor network, and constructing a traffic map and a speed observation sequence; S2, enabling the coding end to carry out feature transformation on original node features; S3, carrying out node space feature fusion; S4, modeling dynamic time sequence characteristics in the network based on the bidirectional time sequence space coding layer; S5, enabling the decoding end to perform feature transformation on the original node features; S6, learning coding time sequence features of the splicing features based on a bidirectional GRU layer; and S7, based on the timing sequence multi-head attention layer, calculating the attention between the state of the current moment and a plurality of observation states of the coding end, and performing prediction. According to the method, the modeling problem of the time sequence characteristics and the spatial characteristics in the time sequence traffic network of the static topology is solved, the capturing capability of the traffic speed prediction model on the spatial characteristics and the time sequence dependence characteristics is improved based on the time sequence diagram neural network, and the method has good availability.

The invention discloses a time sequence diagram-based public security knowledge graph generation method for generic perception data. Comprising the following steps: preprocessing original collected data: extracting features and calculating various attribute information for original data information collected by a generic perception data link; entity linking: acquiring information of the processed generic perception data link, retrieving on the constructed atlas, and judging whether the entity which the generic perception data link belongs to exists or not; performing knowledge reasoning to generate a time sequence diagram; performing knowledge processing and conflict solving; and updating knowledge reasoning and generating a time sequence diagram according to the knowledge graph. According to the invention, the time dimension is introduced into the atlas, and good access performance aiming at specific time points, vertexes, edges and attached data is provided, so that real-time prevention and control are more effectively realized.

The invention relates to a software reliability testing method and device based on code tracking, belongs to the technical field of software testing, and solves the problems that in the prior art, code tracking is lacked, and static information extraction is not suitable for detecting the consistency of a model and a code. The method comprises the steps of tracking from a reliability strategy model to the code to obtain a reliability strategy code, wherein tracking comprises positioning and mapping; acquiring a Log file based on reliability strategy code instrumentation, wherein the Log filecomprises execution path information of the reliability strategy code; constructing a code LTS based on the Log file; constructing a reliability strategy UML time sequence diagram model; converting the reliability strategy UML time sequence diagram model into a model LTS; extracting branch paths of the code LTS as code paths, and extracting all branch paths of the model LTS as model paths; and judging whether the model path is matched with the code path. Code tracking and an accurate model and code dynamic consistency checking method are realized.

The invention provides a method for establishing a time sequence diagram in parallel based on geometrical information. The method comprises the following steps of conducting the geometrical block division on a circuit diagram according to geometrical characteristics of the circuit diagram; starting a plurality of processes, and establishing a temporary time sequence diagram in each geometric blockin parallel; and splicing the temporary time sequence diagrams established in the geometric blocks into a complete time sequence diagram. According to the method for establishing the time sequence diagram in parallel based on the geometrical information, a plurality of processes can be started to establish the time sequence diagram in parallel for the geometrical blocks, the method can be easilyimplemented by a distributed system, and the time for establishing the time sequence diagram in static time sequence analysis is greatly shortened.

The invention discloses a knowledge graph element organization method oriented to a time sequence tangent plane. The method comprises the steps of defining a maximum effective time range of a system;organizing entities and relationships, and constructing a time sequence map; obtaining a key point set; and obtaining the tangent plane of the time sequence map, and determining the entity, the relationship and all change processes of the attributes of the entity and the relationship in the effective time range, or the attribute values and states of the entity and the relationship in the key points. The method can reflect the storage time ranges of the vertexes and the edges, the attributes of the vertexes and the edges in different time ranges and the change conditions of the vertexes and theedges, and unified version division is not needed; the state of the atlas at any moment within the effective time range of the atlas can be obtained, all states of a certain graph element are directly obtained, and compared with an incremental graph method, calculation steps are greatly reduced.

The invention provides an analysis and optimization method for abnormal data in slope deformation monitoring, which comprises the following steps of S1, converting side slope monitoring measured data into a plurality of arrays containing a time sequence, and drawing a measured value time sequence diagram; S2, inputting any array into the slope monitoring data prediction model for prediction; S3, drawing a predicted value time sequence diagram; S4, calculating a difference value between the slope monitoring measured data and the predicted data according to the measured value and the predicted value time sequence diagram, and taking the corresponding slope monitoring measured data when the difference value is greater than a threshold value as abnormal data; and S5, deleting the abnormal data in the array, and filling the array with the slope monitoring prediction data corresponding to the time sequence of the abnormal data on the prediction value time sequence diagram. The technical problems that abnormal data of slope deformation monitoring are not analyzed and optimized, and the abnormal data can interfere with a later data processing process can be solved.

The invention relates to the technical field of object-oriented software system integration testing and provides an integration testing module priority ranking method based on a UML model. The methodcomprises the following steps: firstly, converting an object-oriented software system UML time sequence diagram into a finite state automaton; then, calculating threatening, vulnerability and failureconsequences of a message, and calculating a weight of the message based on a probability risk assessment method; and finally, calculating the PageRank values of test modules, sorting the priorities of the test modules according to the PageRank values of the test modules, wherein the higher the PageRank values are, the higher the priorities of the test modules are. According to the method, the calculation complexity of priority ranking of the integrated test module can be reduced, the calculation cost is reduced, and the calculation efficiency is improved.

The invention relates to an integrated circuit, discloses a time sequence bottleneck node analysis and time sequence optimization method and system in the integrated circuit, and greatly reduces the calculation amount of time sequence bottleneck analysis on the premise of ensuring the accuracy of the time sequence bottleneck analysis. The method comprises the steps of obtaining a time sequence diagram of an integrated circuit; performing forward breadth-first traversal on the time sequence diagram from the starting point of a time sequence path, and calculating the preorder time sequence criticality of each node in the time sequence diagram; performing reverse breadth-first traversal on the time sequence diagram from the end point of the time sequence path, and calculating the post-sequence time sequence criticality of each node in the time sequence diagram; for each node, calculating the product of the preorder time sequence criticality of the node and the subsequent time sequence criticality of the node as the comprehensive time sequence criticality of the node; and determining a time sequence bottleneck node according to the comprehensive time sequence criticality of each node.

The invention discloses a micro-service design method and system based on a business process model. The method comprises the following steps: firstly, converting a business process diagram into a BPMN engineering model; then converting the BPMN engineering model into an SSD engineering model by using a conversion strategy; converting the SSD engineering model into an SSD time sequence diagram by using a visualization rule; and finally, analyzing the SD engineering model by using a conversion rule to carry out micro-service design. According to the invention, the micro-service design scheme can be automatically generated from the BPMN graph, a designer is assisted in rapidly designing a system, and the design cost is saved; codes can be automatically generated from the SD engineering model, developers are assisted in rapidly developing systems meeting user requirements, and the development cost is greatly reduced.

The invention discloses a time sequence diagram annotation processing system and method, and the system comprises an annotation module and a control module, the control module is used for receiving aninstruction and analyzing the instruction, calling the annotation module to generate an annotation icon when the analyzed instruction is an annotation instruction, and carrying out the annotation operation of a time sequence diagram through employing the annotation icon; wherein the annotation icon comprises an annotation title box, an annotation dragging button, an annotation pointing line and an annotation pointing dragging button, the annotation title box is arranged around the annotation dragging button, one end of the annotation pointing line is connected with the annotation dragging button, and the other end of the annotation pointing line is connected with the annotation pointing dragging button; wherein the annotation title box is used for inputting names and/or descriptions of annotations by a user and displaying the input names and/or simple descriptions; wherein the annotation dragging button is used for dragging an annotation icon and setting the attribute of the annotation icon by a user; wherein the annotation pointing line is used for pointing to the component to which the annotation aims; the annotation pointing drag button is used for being dragged by a user to modify the specific pointing direction of the annotation pointing line.

The invention relates to a reliability strategy model and code consistency detection method and device, belongs to the technical field of software testing, and solves the problem that existing staticinformation extraction is not suitable for detecting the consistency of a model and a code. The method comprises the following steps: constructing a reliability strategy UML time sequence diagram model; converting the reliability strategy UML time sequence diagram model into a model LTS; tracking the reliability strategy model to the code to obtain a reliability strategy code; obtaining a Log filebased on reliability strategy code instrumentation, wherein the Log file comprises execution path information of the reliability strategy code; constructing a code LTS based on the Log file; extracting all branch paths of the model LTS as model paths, and extracting branch paths of the code LTS as code paths; detecting the consistency between the model path and the code path; and when the numberof the code paths is greater than or equal to the minimum number of the code paths, determining that the consistency detection result is accurate. According to the invention, an accurate dynamic consistency checking method for the model and the code is realized.