Time sequence bottleneck node analysis and time sequence optimization method and system in integrated circuit

Abstract

The invention relates to an integrated circuit, discloses a time sequence bottleneck node analysis and time sequence optimization method and system in the integrated circuit, and greatly reduces the calculation amount of time sequence bottleneck analysis on the premise of ensuring the accuracy of the time sequence bottleneck analysis. The method comprises the steps of obtaining a time sequence diagram of an integrated circuit; performing forward breadth-first traversal on the time sequence diagram from the starting point of a time sequence path, and calculating the preorder time sequence criticality of each node in the time sequence diagram; performing reverse breadth-first traversal on the time sequence diagram from the end point of the time sequence path, and calculating the post-sequence time sequence criticality of each node in the time sequence diagram; for each node, calculating the product of the preorder time sequence criticality of the node and the subsequent time sequence criticality of the node as the comprehensive time sequence criticality of the node; and determining a time sequence bottleneck node according to the comprehensive time sequence criticality of each node.

Description

technical field [0001] The present application relates to integrated circuits, and in particular to timing optimization techniques for integrated circuits. Background technique [0002] This section is intended to provide a background or context for the embodiments of the application that are recited in the claims. The description herein is not an admission that it is disclosed prior art by inclusion in this section. [0003] Timing is a critical element of integrated circuits (also known as chips). The integrated circuit that meets the timing requirements can work normally, and the timing also determines the operating frequency of the integrated circuit, and the operating frequency is a decisive factor in the performance of the integrated circuit. [0004] Through a comprehensive analysis of the integrated circuit, the timing bottleneck of the integrated circuit is identified, and then timing optimization is performed for the timing bottleneck, which can effectively impro...

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Problems solved by technology

[0005] However, exhaustively enumerating the critical timing paths in an integrated circuit is very inefficient; as the size of the chip increases, the runtime required for exhaustive methods increases exponentially

That is to say, when the scale of the chip reaches a certain level, the exhaustive method cannot be completed in a reasonable time due to the large amount of calculation.

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